JAJSF94F July   2015  – May 2018 SN65DP159 , SN75DP159

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      DP159マザーボード・アプリケーションの構造
      2.      DP159ドングル・アプリケーションの構造
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Supply Electrical Characteristics
    6. 7.6  Differential Input Electrical Characteristics
    7. 7.7  HDMI and DVI TMDS Output Electrical Characteristics
    8. 7.8  AUX, DDC, and I2C Electrical Characteristics
    9. 7.9  HPD Electrical Characteristics
    10. 7.10 HDMI and DVI Main Link Switching Characteristics
    11. 7.11 AUX Switching Characteristics (Only for RGZ Package)
    12. 7.12 HPD Switching Characteristics
    13. 7.13 DDC and I2C Switching Characteristics
    14. 7.14 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Reset Implementation
      2. 9.3.2 Operation Timing
      3. 9.3.3 I2C-over-AUX to DDC Bridge (SNx5DP159 48-Pin Package Version Only)
      4. 9.3.4 Input Lane Swap and Polarity Working
      5. 9.3.5 Main Link Inputs
      6. 9.3.6 Main Link Inputs Debug Tools
      7. 9.3.7 Receiver Equalizer
      8. 9.3.8 Termination Impedance Control
      9. 9.3.9 TMDS Outputs
        1. 9.3.9.1 Pre-Emphasis/De-Emphasis
    4. 9.4 Device Functional Modes
      1. 9.4.1 Retimer Mode
      2. 9.4.2 Redriver Mode
      3. 9.4.3 DDC Training for HDMI2.0 Data Rate Monitor
      4. 9.4.4 DDC Functional Description
    5. 9.5 Register Maps
      1. 9.5.1 DP-HDMI Adaptor ID Buffer
      2. 9.5.2 Local I2C Interface Overview
      3. 9.5.3 I2C Control Behavior
      4. 9.5.4 I2C Control and Status Registers
        1. 9.5.4.1 Bit Access Tag Conventions
        2. 9.5.4.2 CSR Bit Field Definitions
          1. 9.5.4.2.1 ID Registers
          2. 9.5.4.2.2 Misc Control
          3. 9.5.4.2.3 HDMI Control
          4. 9.5.4.2.4 Equalization Control Register
          5. 9.5.4.2.5 EyeScan Control Register
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Use Case of SNx5DP159
      2. 10.1.2 DDC Pullup Resistors
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
    3. 10.3 System Example
      1. 10.3.1 Compliance Testing
  11. 11Power Supply Recommendations
    1. 11.1 Power Management
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
    3. 12.3 Thermal Considerations
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 関連リンク
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

11.1 Power Management

To minimize the power consumption of customer application, SNx5DP159 uses dual power supply. VCC is 3.3-V with 10% range to support the I/O voltage. The VDD is 1.00-V to 1.27-V range to supply the internal digital control circuit. v operates in two different working states. See Table 14 for conditions for each mode. When OE is deasserted and then reasserted the device will rest to its default configurations. If different configurations were programmed using I2C then the device will have to be reprogrammed.

  • Power-down mode:
    • OE = Low puts the device into its lowest power state by shutting down all function blocks
      • When OE is re-asserted the transitions from L → H will create a reset and if the device is programmed through I2C it will have to be reprogrammed.
      • OE = High, HPD_SNK = Low
      • Writing a 1 to register 09h[3]
  • Normal operation: Working in redriver or retimer
  • When HPD asserts, the device CDR and output will enable based on the signal detector circuit result
  • HPD_SRC = HPD_SNK in all conditions. The HPD channel operational when VCC over 3-V.

NOTE

When the SNx5DP159 is put into a power down state using the OE pin the I2C registers are cleared. The TMDS_CLOCK_RATIO_STATUS bit will be cleared in all power down states. If cleared and HDMI2.0 resolutions are to be supported, the SNx5DP159 expects the source to write a 1 to this bit location. If this does not happen the PLL will not be set properly and no video may be evident.

Table 14. Control Logic and Mode of Operation

INPUTS(1) STATUS MODE
HPD_SNK OE Mode of Operation HPD_SRC IN_Dx SDA_CTL
SCL_CTL		 OUT_Dx
OUT_CLK		 DDC AUX_SRC±
(48 PIN ONLY)
H L X H High-Z Disabled High-Z Disabled Disable Power-down mode
L H X L High-Z Active High-Z Disabled Disable Power-down mode
H H X H High-Z Active High-Z Disabled Disable Power-down mode when a one is written to 09h[3]
H H Redriver H RX active Active TX active Active Active Normal operation
H H Retimer H RX active Active TX active Active Active Normal operation
(1) L = LOW, H = HIGH

TMDS output termination control impacts the operating power.

Table 15. Control Logic and Mode of Operation

INPUTS(1) STATUS MODE
HPD_SNK OE Mode of Operation HPD_SRC IN_Dx SDA_CTL
SCL_CTL		 OUT_Dx
OUT_CLK		 DDC
H L X H High-Z Disabled High-Z Disabled Power-down mode
L H X L High-Z Active High-Z Disabled Power-down mode
H H X H High-Z Active High-Z Disabled Power-down mode when a one is written to 09h[3]
H H Redriver H RX active Active TX active Active Normal operation
H H Retimer H RX active Active TX active Active Normal operation
(1) L = LOW, H = HIGH

TMDS output termination control impacts the operating power.