JAJSFC3A April   2018  – December 2018 TPS563249

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      TPS563249の効率
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Adaptive On-Time Control and PWM Operation
      2. 7.3.2 Soft Start and Pre-Biased Soft Start
      3. 7.3.3 Current Protection
      4. 7.3.4 Undervoltage Lockout (UVLO) Protection
      5. 7.3.5 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Standby Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Voltage Resistors Selection
        2. 8.2.2.2 Output Filter Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Bootstrap Capacitor Selection
        5. 8.2.2.5 Dropout
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

8.2.2.2 Output Filter Selection

The LC filter used as the output filter has double pole at:

Equation 2. TPS563249 Eq_03_SLVSD90.gif

At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the device. The low frequency phase is 180°. At the output filter pole frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. D-CAP3 introduces a high frequency zero that reduces the gain roll off to –20 dB per decade and increases the phase to 90° one decade above the zero frequency. The inductor and capacitor for the output filter must be selected so that the double pole of Equation 2 is located below the high frequency zero but close enough that the phase boost provided by the high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the values recommended in Table 2.

Table 2. Recommended Component Values

OUTPUT VOLTAGE (V) R1 (kΩ) R2 (kΩ) L1 (µH) C8 + C9 (µF)
MIN TYP MAX
1 6.65 10.0 0.33 0.56 1 10 to 44
1.05 7.5 10.0 0.33 0.56 1 10 to 44
1.2 10 10.0 0.47 0.68 1.5 10 to 44
1.5 15 10.0 0.47 0.82 1.5 10 to 44
1.8 20 10.0 0.56 1 2.2 10 to 44
2.5 31.6 10.0 0.68 1 2.2 10 to 44
3.3 45.3 10.0 0.82 1.5 3.3 10 to 44
5 73.2 10.0 1 1.5 3.3 10 to 44
6.5 97.6 10.0 1 1.5 3.3 10 to 44

The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 3, Equation 4, and Equation 5. The inductor saturation current rating must be greater than the calculated peak current and the RMS or heating current rating must be greater than the calculated RMS current.

Equation 3. TPS563249 Eq_04_SLVSD90.gif
Equation 4. TPS563249 Eq_05_SLVSD90.gif
Equation 5. TPS563249 Eq_06_SLVSD90.gif

For this design example, the calculated peak current is 3.63 A and the calculated RMS current is 3.02 A. The inductor used is a WE 744311150 with a rated current of 11 A.

The capacitor value and ESR determines the amount of output voltage ripple. The TPS563249 is intended for use with ceramic or other low ESR capacitors. Recommended values range from 10 µF to 44 µF. Use Equation 6 to determine the required RMS current rating for the output capacitor.

Equation 6. TPS563249 Eq_07_SLVSD90.gif

For this design one Murata GRM31CR61A226KE19 22-µF output capacitor is used. The typical ESR is 2 mΩ. The calculated RMS current is 0.365 A and output capacitor is rated for 4 A.