JAJSFC6C May 2015 – April 2018 ADS52J90
PRODUCTION DATA.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
FORCE_LMFC_COUNT | LMFC_COUNTER_INIT_VALUE | 0 | 0 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | FORCE_LMFC_COUNT | R/W | 0h | 0 = Default value
1 = The LMFC counter value is forced, as per register 120, bits 14-10. |
14-10 | LMFC_COUNTER_INIT_VALUE | R/W | 0h | These bits specify the initial value of the LMFC counter. This option is useful when the multiframe size must be different than the default value; see the Synchronization Using SYNC~ and SYSREF section. |
9-0 | 0 | R/W | 0h | Must write 0 |