JAJSFC6 データシート

JAJSFC6C May 2015 – April 2018 ADS52J90

PRODUCTION DATA.

8.3.11 Clock Input

The input clock to the device (referred to as the system clock) goes to an input buffer that automatically configures itself either to accept a single-ended clock or a differential clock. The equivalent load on the clock pins in the case of a differential clock input is shown in Figure 85. For the case of a single-ended clock input, the 5-kΩ resistor is disconnected from the input.

Figure 85. Internal Clock Buffer for Differential Clock Mode

If the preferred clocking scheme for the device is single-ended, connect the CLKM pin to ground (in other words, short CLKM directly to AVSS, as shown in Figure 86). In this case, the auto-detect feature shuts down the internal differential clock buffer and the device automatically goes into a single-ended clock input. Connect the single-ended clock source directly (without decoupling) to the CLKP pin. When using a single-ended clock input, TI recommends using low-jitter, square signals (LVCMOS levels, 1.8-V amplitude) to drive the ADC (refer to technical brief, Clocking High-Speed Data Converters, SLYT075 for further details).

Figure 86. Single-Ended Clock Driving Circuit

For differential clocks (such as differential sine-wave, LVPECL, LVDS, and so forth), enable the clock amplifier with the connection scheme shown in Figure 87. This same scheme applies when the clock is single-ended but the clock amplitude is either small or its edges are not sharp. In this case, connect the input clock signal with a capacitor to CLKP (as in Figure 87) and connect CLKM to ground through a capacitor (that is, ac-coupled to AVSS).

If a transformer is used with the secondary coil floating (for instance, to convert from single-ended to differential), the outputs of the transformer can be connected directly to the clock inputs without requiring the 10-nF series capacitors.

ADS52J90 ai_drv_cir_differential_bas623.gif

Figure 87. Differential Clock Driving Circuit

To ensure that the aperture delay and jitter are the same for all channels, the device uses a clock tree network to generate individual sampling clocks for each channel. For all channels, the clock is closley matched from the source point to the sampling circuit of each of the eight internal devices.

The jitter cleaners CDCM7005, CDCE72010, or LMK048X series are suitable to generate the system clock and enable high performance. Figure 88 shows a clock distribution network.

Figure 88. System Clock Distribution Network