JAJSFC6C May 2015 – April 2018 ADS52J90
PRODUCTION DATA.
Mapping of the analog inputs to the LVDS outputs is shown in Table 38 for a case corresponding to a 32-input mode and a 1X data rate.
ANALOG INPUT SIGNAL | CONNECTION TO ANALOG INPUT PINS | SAMPLING INSTANT | ADC WORD | SERIAL_OUT
(Over One Frame) |
LVDS OUTPUTS ON DOUT PINS |
---|---|---|---|---|---|
AIN1 | IN1 | t1 | ADCOUT1o | ADCOUT1o,
ADCOUT1e |
DOUT1 |
AIN2 | IN2 | t2 | ADCOUT1e | ||
AIN3 | IN3 | t1 | ADCOUT2o | ADCOUT2o,
ADCOUT2e |
DOUT2 |
AIN4 | IN4 | t2 | ADCOUT2e | ||
AIN5 | IN5 | t1 | ADCOUT3o | ADCOUT3o,
ADCOUT3e |
DOUT3 |
AIN6 | IN6 | t2 | ADCOUT3e | ||
AIN7 | IN7 | t1 | ADCOUT4o | ADCOUT4o,
ADCOUT4e |
DOUT4 |
AIN8 | IN8 | t2 | ADCOUT4e | ||
AIN9 | IN9 | t1 | ADCOUT5o | ADCOUT5o,
ADCOUT5e |
DOUT5 |
AIN10 | IN10 | t2 | ADCOUT5e | ||
AIN11 | IN11 | t1 | ADCOUT6o | ADCOUT6o,
ADCOUT6e |
DOUT6 |
AIN12 | IN12 | t2 | ADCOUT6e | ||
AIN13 | IN13 | t1 | ADCOUT7o | ADCOUT7o,
ADCOUT7e |
DOUT7 |
AIN14 | IN14 | t2 | ADCOUT7e | ||
AIN15 | IN15 | t1 | ADCOUT8o | ADCOUT8o,
ADCOUT8e |
DOUT8 |
AIN16 | IN16 | t2 | ADCOUT8e | ||
AIN17 | IN17 | t1 | ADCOUT9o | ADCOUT9o,
ADCOUT9e |
DOUT9 |
AIN18 | IN18 | t2 | ADCOUT9e | ||
AIN19 | IN19 | t1 | ADCOUT10o | ADCOUT10o,
ADCOUT10e |
DOUT10 |
AIN20 | IN20 | t2 | ADCOUT10e | ||
AIN21 | IN21 | t1 | ADCOUT11o | ADCOUT11o,
ADCOUT11e |
DOUT11 |
AIN22 | IN22 | t2 | ADCOUT11e | ||
AIN23 | IN23 | t1 | ADCOUT12o | ADCOUT12o,
ADCOUT12e |
DOUT12 |
AIN24 | IN24 | t2 | ADCOUT12e | ||
AIN25 | IN25 | t1 | ADCOUT13o | ADCOUT13o,
ADCOUT13e |
DOUT13 |
AIN26 | IN26 | t2 | ADCOUT13e | ||
AIN27 | IN27 | t1 | ADCOUT14o | ADCOUT14o,
ADCOUT14e |
DOUT14 |
AIN28 | IN28 | t2 | ADCOUT14e | ||
AIN29 | IN29 | t1 | ADCOUT15o | ADCOUT15o,
ADCOUT15e |
DOUT15 |
AIN30 | IN30 | t2 | ADCOUT15e | ||
AIN31 | IN31 | t1 | ADCOUT16o | ADCOUT16o,
ADCOUT16e |
DOUT16 |
AIN32 | IN32 | t2 | ADCOUT16e |
Note that 2X data rate mode is not supported in 32-input mode. In 32-input mode, only one ADC is used to convert two inputs.
The odd numbered inputs correspond to the odd sample from the ADC, and the even numbered inputs correspond to the even sample from the ADC. The register map relative to the ADCs can therefore be mapped to the 32 channels, as shown in Table 39.
REGISTER MAP NOTATION | MAPPING TO CHANNELS IN 16-INPUT MODE | EXAMPLE |
---|---|---|
GAIN_ADCxo | GAIN_CHANNEL (odd) | GAIN_CHANNEL1 = GAIN_ADC1o |
GAIN_ADCxe | GAIN_CHANNEL (even) | GAIN_CHANNEL2 = GAIN_ADC1e |
OFFSET_ADCXo | OFFSET_CHANNEL (odd) | OFFSET_CHANNEL1 = OFFSET_ADC1o |
OFFSET_ADCxe | OFFSET_CHANNEL (even) | OFFSET_CHANNEL2 = OFFSET_ADC1e |
PDN_DIG_ADCx | PDN_DIG_CHANNEL (odd and even) | PDN_DIG_CHANNEL1 = PDN_DIG_CHANNEL2 = PDN_DIG_ADC1 |
PDN_ANA_ADCx | PDN_ANA_CHANNEL (odd and even) | PDN_ANA_CHANNEL1 = PDN_ANA_CHANNEL2 = PDN_ANA_ADC1 |
DIG_HPF_EN_ADCx | Mapped to 8 channels | DIG_HPF_EN_CHANNEL1-8 = DIG_HPF_EN_ADC1-4
Common setting for 4 ADCs mapped to common setting for 8 channels |
HPF_CORNER_ADCx | Mapped to 8 channels | HPF_CORNER_CHANNEL1-8 = HPF_CORNER_ADC1-4
Common setting for 4 ADCs mapped to common setting for 8 channels |