15-13 |
SER_DATA_RATE |
R/W |
0h |
These bits control the LVDS serialization rate.
000 = 12X
001 = 14X
100 = 16X
011 = 10X
101, 110, 111, 010 = Unused |
12 |
DIG_GAIN_EN |
R/W |
0h |
0 = Digital gain disabled
1 = Digital gain enabled |
11 |
0 |
R/W |
0h |
Must write 0 |
10-9 |
OFFSET_CORR_DELAY_FROM_
TX_TRIG[7:6] |
R/W |
0h |
This is a part of an 8-bit control that initiates offset correction after the TX_TRIG input pulse (each step is equivalent to one sample delay); the remaining six LSB bits are the OFFSET_CORR_DELAY_FROM_TX_TRIG[5:0] bits (bits 5-0) in register 2. |
8 |
DIG_OFFSET_EN |
R/W |
0h |
0 = Digital offset subtraction disabled
1 = Digital offset subtraction enabled |
7-6 |
0 |
R/W |
0h |
Must write 0 |
5 |
JESD_WR_SEL |
R/W |
0h |
0 = Setting when writing to all registers except for registers with addresses in the decimal range of 115-119 and 134-138
1 = Setting when writing to registers with addresses in the decimal range of 115-119 and 134-138 |
4-0 |
0 |
R/W |
0h |
Must write 0 |