JAJSFC7C September   2015  – July 2016 SN65DP149 , SN75DP149

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      DP149マザーボード・アプリケーションの構造
      2.      DP149ドングル・アプリケーションの構造
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Supply Electrical Characteristics
    6. 7.6  Differential Input Electrical Characteristics
    7. 7.7  HDMI and DVI TMDS Output Electrical Characteristics
    8. 7.8  DDC, and I2C Electrical Characteristics
    9. 7.9  HPD Electrical Characteristics
    10. 7.10 HDMI and DVI Main Link Switching Characteristics
    11. 7.11 HPD Switching Characteristics
    12. 7.12 DDC and I2C Switching Characteristics
    13. 7.13 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Reset Implementation
      2. 9.3.2 Operation Timing
      3. 9.3.3 Input Lane Swap and Polarity Working
      4. 9.3.4 Main Link Inputs
      5. 9.3.5 Main Link Inputs Debug Tools
      6. 9.3.6 Receiver Equalizer
      7. 9.3.7 Termination Impedance Control
      8. 9.3.8 TMDS Outputs
        1. 9.3.8.1 Pre-Emphasis/De-Emphasis
    4. 9.4 Device Functional Modes
      1. 9.4.1 Retimer Mode
      2. 9.4.2 Redriver Mode
      3. 9.4.3 DDC Functional Description
    5. 9.5 Register Maps
      1. 9.5.1 DP-HDMI Adaptor ID Buffer
      2. 9.5.2 Local I2C Interface Overview
      3. 9.5.3 I2C Control Behavior
      4. 9.5.4 I2C Control and Status Registers
        1. 9.5.4.1 Bit Access Tag Conventions
        2. 9.5.4.2 CSR Bit Field Definitions
          1. 9.5.4.2.1 ID Registers
          2. 9.5.4.2.2 Misc Control
          3. 9.5.4.2.3 HDMI Control
          4. 9.5.4.2.4 Equalization Control Register
          5. 9.5.4.2.5 EyeScan Control Register
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Use Case of SNx5DP149
      2. 10.1.2 DDC Pullup Resistors
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 System Example
      1. 10.3.1 Compliance Testing
  11. 11Power Supply Recommendations
    1. 11.1 Power Management
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 関連リンク
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

9.5.4.2.5 EyeScan Control Register

Table 10. EyeScan Control Register

ADDRESS BITS DEFAULT DESCRIPTION ACCESS
0Eh 7:4 4’b0000 PV_SYNC[3:0]. Pattern timing pulse. This field is updated for 8UI once every cycle of the PRBS generator. 1 bit per lane. R
3:0 4’b0000 PV_LD[3:0]. Load pattern-verifier controls into RX lanes. When asserted high, the PV_TO, PV_SEL, PV_LEN, PV_CP20, and PV_CP values are enabled into the corresponding RX lane. These values are then latched and held when PV_LD[n] is subsequently de-asserted low. 1 bit per lane. RWU
0Fh 7:4 4’b0000 PV_FAIL[3:0]. Pattern verification mismatch detected. 1 bit per lane. RU
3:0 4’b0000 PV_TIP[3:0]. Pattern search/training in progress. 1 bit per lane. RU
10h 7 1’b0 PV_CP20. Customer pattern length 20 or 16 bits.
0 – 16 bits
1 – 20 bits		 RW
6 1’b0 Reserved R
5:3 3’b000 PV_LEN[2:0]. PRBS pattern length
000 – PRBS7
001 – PRBS11
010 – PRBS23
011 – PRBS31
100 – PRBS15
101 – PRBS15
110 – PRBS20
111 – PRBS20		 RW
2:0 3’b000 PV_SEL[24:0]. Pattern select control
000 – Disabled
001 – PRBS
010 – Clock
011 – Custom
1xx – Timing only mode with sync pulse spacing defined by PV_LEN		 RW
11h 7:0 ‘h00 PV_CP[7:0]. Custom pattern data. RW
12h 7:0 ‘h00 PV_CP[15:8]. Custom pattern data. RW
13h 7:4 4’b0000 Reserved R
3:0 4’b0000 PV_CP[19:16]. Custom pattern data. Used when PV_CP20 = 1’b1. RW
14h 7:3 5’b00000 Reserved R
2:0 3’b000 PV_THR[2:0]. Pattern-verifier retain threshold. RW
15h 7 1'b0 DESKEW_CMPLT: Indicates TMDS lane deskew has completed when high R
6:5 2’b00 Reserved R
4 1’b0 BERT_CLR. Clear BERT counter (on rising edge). RSU
3 1’b0 TST_INTQ_CLR. Clear latched interrupt flag. RSU
2:0 3’b000 TST_SEL[2:0]. Test interrupt source select. RW
16h 7:4 4’b0000 PV_DP_EN[3:0]. Enabled datapath verified based on DP_TST_SEL, 1 bit per lane. RW
3 1’b0 Reserved R
2:0 3'b000 DP_TST_SEL[2:0] Selects pattern reported by BERT_CNT[11:0], TST_INT[0] and TST_INTQ[0]. PV_DP_EN is non-zero
000 – TMDS disparity or data errors
001 – FIFO errors
010 – FIFO overflow errors
011 – FIFO underflow errors
100 – TMDS deskew status
101 – Reserved
110 – Reserved
111 – Reserved		 RW
17h 7:4 4’b0000 TST_INTQ[3:0]. Latched interrupt flag. 1 bit per lane RU
3:0 4’b0000 TST_INT[3:0]. Test interrupt flag. 1 bit per lane. RU
18h 7:0 ‘h00 BERT_CNT[7:0]. BERT error count. Lane 0 RU
19h 7:4 4’b0000 Reserved R
3:0 4’b0000 BERT_CNT[11:8]. BERT error count. Lane 0 RU
1Ah 7:0 ‘h00 BERT_CNT[19:12]. BERT error count. Lane 1 RU
1Bh 7:4 4’b0000 Reserved R
3:0 4’b0000 BERT_CNT[23:20]. BERT error count. Lane 1 RU
1Ch 7:0 ‘h00 BERT_CNT[31:24]. BERT error count. Lane 2 RU
1Dh 7:4 4’b0000 Reserved R
3:0 4’b0000 BERT_CNT[35:32]. BERT error count. Lane 2 RU
1Eh 7:0 ‘h00 BERT_CNT[19:12]. BERT error count. Lane 3 RU
1Fh 7:4 4’b0000 Reserved R
3:0 ‘h00 BERT_CNT[23:20]. BERT error count. Lane 3 RU
20h 7 1'b0 Power Down Status Bit
0 – Normal Operation
1 – Device in Power Down Mode 		R
6 1'b0 Standby Status Bit
0 – Normal Operation
1 – Device in Standby Mode 		R
5:0 6'b000000 Reserved R