JAJSFC7C September 2015 – July 2016 SN65DP149 , SN75DP149
PRODUCTION DATA.
The SNx5DP149 can be designed into many types of applications. All applications have certain requirements for the system to work properly. Two voltage rails are required to support the lowest possible power consumption. The OE pin must have a 0.1-µF capacitor to ground. This pin can be driven by a processor but the pin needs to change states after voltage rails have stabilized. Configure the device by using I2C. Pin strapping is provided as I2C is not available in all cases. Because sources may have different naming conventions, confirm the link between the source and the SNx5DP149 is correctly mapped. A swap function is provided for the input pins in case signaling is reversed between the source and the device. For the control pins the values provided below are when they are being controlled by a micro-controller. If this is not the case then using the 65-kΩ for a pull up for high, pulled down for low, and left floating for mid level.
DESIGN PARAMETER | VALUE |
---|---|
VCC | 3.3 V |
VDD | 1.1 V |
Main link input voltage | VID = 75 mVpp to 1.2 Vpp |
Control pin Low | 65-kΩ pulled to GND |
Control pin Mid | No Connect |
Control pin High | 65-kΩ pulled to 3.3-V |
Vsadj resistor | 7.06-kΩ |
Main link AC decoupling capacitor | 75 to 200 nF, recommend 100 nF |