JAJSFE6I July 2009 – May 2018 TPS65070 , TPS65072 , TPS65073 , TPS650731 , TPS650732
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
WLED_CTRL2 | B7 | B6 | B5 | B4 | B3 | B2 | B1 | BO |
---|---|---|---|---|---|---|---|---|
Bit name and function | Current level | LED DUTY CYCLE_6 | LED DUTY CYCLE_5 | LED DUTY CYCLE_4 | LED DUTY CYCLE_3 | LED DUTY CYCLE_2 | LED DUTY CYCLE_1 | LED DUTY CYCLE_0 |
Default | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |
Default value loaded by: | UVLO | UVLO | UVLO | UVLO | UVLO | UVLO | UVLO | UVLO |
Read/write | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
Bit 7 | CURRENT LEVEL:
0 = current defined with resistor connected from ISET2 to GND 1 = current defined with resistor connected from ISET1 to GND |
Bit 6..0 | sets the duty cycle for PWM dimming from 1% (0000000) to 100% (1100011).
Values above 1100011 set the duty cycle to 0 %; default is 30% duty cycle |