JAJSFE6I July 2009 – May 2018 TPS65070 , TPS65072 , TPS65073 , TPS650731 , TPS650732
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
The TPS6507x step down converters operate with typically 2.25-MHz fixed-frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents the converter automatically enters power save mode and operates in pulse frequency modulation (PFM).
During PWM operation the converter use a unique fast response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the high side MOSFET switch is turned on. The current flows now from the input capacitor through the high side MOSFET switch through the inductor to the output capacitor and load. During this phase, the current ramps up until the PWM comparator trips and the control logic will turn off the switch. The current limit comparator will also turn off the switch in case the current limit of the high side MOSFET switch is exceeded. After a dead time preventing shoot through current, the low side MOSFET rectifier is turned on and the inductor current will ramp down. The current flows now from the inductor to the output capacitor and to the load. It returns back to the inductor through the low side MOSFET rectifier.
The next cycle will be initiated by the clock signal again turning off the low side MOSFET rectifier and turning on the on the high side MOSFET switch.
The DC-DC converters operate synchronized to each other, with converter 1 as the master. A phase shift of 180° between converter 1 and converter 2 decreases the input RMS current. Therefore smaller input capacitors can be used. Converter 3 operates in phase with converter 1.