JAJSFG3C may   2018  – may 2023 ADC12DL3200

PRODUCTION DATA  

  1.   1
  2. 1特長
  3. 2アプリケーション
  4. 3概要
  5. 4Revision History
  6. 5Pin Configuration and Functions
  7. 6Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  8. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Analog Input Protection
        2. 7.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.1.3 Analog Input Offset Adjust
      2. 7.3.2 ADC Core
        1. 7.3.2.1 ADC Theory of Operation
        2. 7.3.2.2 ADC Core Calibration
        3. 7.3.2.3 ADC Overrange Detection
        4. 7.3.2.4 Code Error Rate (CER)
        5. 7.3.2.5 Internal Dither
      3. 7.3.3 Timestamp
      4. 7.3.4 Clocking
        1. 7.3.4.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.4.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.4.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.4.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.4.3.2 Automatic SYSREF Calibration
      5. 7.3.5 LVDS Digital Interface
        1. 7.3.5.1 Multi-Device Synchronization and Deterministic Latency Using Strobes
          1. 7.3.5.1.1 Dedicated Strobe Pins
          2. 7.3.5.1.2 Reduced Width Interface With Dedicated Strobe Pins
          3. 7.3.5.1.3 LSB Replacement With a Strobe
          4. 7.3.5.1.4 Strobe Over All Data Pairs
      6. 7.3.6 Alarm Monitoring
        1. 7.3.6.1 Clock Upset Detection
      7. 7.3.7 Temperature Monitoring Diode
      8. 7.3.8 Analog Reference Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode (Non-DES Mode)
      2. 7.4.2 Internal Dither Modes
      3. 7.4.3 Single-Channel Mode (DES Mode)
      4. 7.4.4 LVDS Output Driver Modes
      5. 7.4.5 LVDS Output Modes
        1. 7.4.5.1 Staggered Output Mode
        2. 7.4.5.2 Aligned Output Mode
        3. 7.4.5.3 Reducing the Number of Strobes
        4. 7.4.5.4 Reducing the Number of Data Clocks
        5. 7.4.5.5 Scrambling
        6. 7.4.5.6 Digital Interface Test Patterns and LVSD SYNC Functionality
          1. 7.4.5.6.1 Active Pattern
          2. 7.4.5.6.2 Synchronization Pattern
          3. 7.4.5.6.3 User-Defined Test Pattern
      6. 7.4.6 Power-Down Modes
      7. 7.4.7 Calibration Modes and Trimming
        1. 7.4.7.1 Foreground Calibration Mode
        2. 7.4.7.2 Background Calibration Mode
        3. 7.4.7.3 Low-Power Background Calibration (LPBG) Mode
      8. 7.4.8 Offset Calibration
      9. 7.4.9 Trimming
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 78
        6. 7.5.1.6 Streaming Mode
        7. 7.5.1.7 80
    6. 7.6 Register Maps
      1. 7.6.1 SPI_REGISTER_MAP Registers
  9.   Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Wideband RF Sampling Receiver
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Input Signal Path
          2. 8.2.1.1.2 Clocking
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Calculating Values of AC-Coupling Capacitors
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Reconfigurable Dual-Channel, 2.5-GSPS or Single-Channel, 5.0-GSPS Oscilloscope
        1. 8.2.2.1 Design Requirements
          1. 8.2.2.1.1 Input Signal Path
          2. 8.2.2.1.2 Clocking
          3. 8.2.2.1.3 The ADC12DL3200
        2. 8.2.2.2 Application Curves
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Sequencing
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 8Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 商標
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  11. 9Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics: DC Specifications

typical values at TA = +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP-DIFF sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in the Recommended Operating Conditions table
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
DC ACCURACY
ResolutionResolution with no missing codes12Bits
DNLDifferential nonlinearityMaximum positive excursion from ideal step size0.3LSB
Maximum negative excursion from ideal step size–0.3
INLIntegral nonlinearityMaximum positive excursion from ideal transfer function1.6LSB
Maximum negative excursion from ideal transfer function–2.0
ANALOG INPUTS (INA±, INB±)
VOFFOffset ErrorCAL_OS = 0±2.0mV
CAL_OS = 1±0.3mV
VOFF_ADJInput offset voltage adjustment rangeAvailable offset correction range (see CAL_OS bit in the CAL_CFGO register or the OADJ_A_FG0_VINA register) ±55 mV
VOFF_ DRIFTOffset driftForeground calibration at nominal temperature only14µV/°C
Foreground calibration at each temperature4
VIN_FSRAnalog differential input full-scale rangeDefault full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000)750800850mVPP
Maximum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xFFFF)10001040
Minimum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0x2000)480525
VIN_FSR_DRIFTAnalog differential input full-scale range driftDefault FS_RANGE_A and FS_RANGE_B setting, foreground calibration at nominal temperature only, inputs driven by 50-Ω source, includes effect of RIN drift0.037%/°C
Default FS_RANGE_A and FS_RANGE_B setting, foreground calibration at each temperature, inputs driven by 50-Ω source, includes effect of RIN drift0.006
VIN_FSR_MATCHAnalog differential input full-scale range matchingMatching between INA± and INB±, default setting, dual channel mode0.53%
RINSingle-ended input resistance to AGNDEach input terminal is terminated to AGND, measured at TA = 25°C485052Ω
RIN_ TEMPCOInput termination linear temperature coefficient13.7mΩ/°C
CINSingle-ended input capacitanceSingle-channel mode measured at DC0.45pF
Dual-channel mode measured at DC0.45
TEMPERATURE DIODE CHARACTERISTICS (TDIODE±)
ΔVBETemperature diode voltage slopeForced forward current of 100 µA. Offset voltage (approximately 0.792 V at 0°C) varies with process and must be measured for each part. Perform offset measurements with the device unpowered or with the PD pin asserted to minimize device self-heating.-1.33mV/°C
BANDGAP VOLTAGE OUTPUT (BG)
VBGReference output voltageIL ≤ 100 µA1.1V
VBG_ DRIFTReference output temperature driftIL ≤ 100 µA–85µV/°C
CLOCK INPUTS (CLK±, SYSREF±, TMSTP±)
ZTInternal terminationDifferential termination with DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN = 0 and TMSTP_LVPECL_EN = 0100Ω
Single ended termination to GND (per pin) with DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN = 0 and TMSTP_LVPECL_EN = 050
VCMInput common-mode voltage, self-biasedSelf-biasing common-mode voltage for CLK± when AC coupled (DEVCLK_LVPECL_EN must be set to 0)0.3V
Self-biasing common-mode voltage for SYSREF± when AC coupled (SYSREF_LVPECL_EN must be set to 0) and with receiver enabled (SYSREF_RECV_EN = 1).0.3
Self-biasing common-mode voltage for SYSREF± when AC coupled (SYSREF_LVPECL_EN must be set to 0) and with receiver disabled (SYSREF_RECV_EN = 0).VA11
CL_DIFFDifferential input capacitanceBetween positive and negative differential input pins0.1pF
CL_SESingle-ended input capacitanceEach input to ground0.5pF
LVDS OUTPUTS (DACLK±, DASTR±, DA[11:0]±, DBCLK±, DBSTR±, DB[11:0]±, DCCLK±, DCSTR±, DC[11:0]±, DDCLK±, DDSTR±, DD[11:0]±)
VDIFFDifferential output peak-to-peak voltage, DC measurementDefault swing (HSM), 100-Ω load400720900mVPP-DIFF
Low swing (LSM), 100-Ω load350
Low swing high-Z mode (HZM), high-impedance load380
VCMOutput common-mode voltage, tracks with VLVDSVLVDS = 1.9 V1.3V
VLVDS = 1.1 V0.5
IOS_DIFFDifferential short-circuit currentPositive and negative outputs shorted together5mA
IOS_GNDShort-circuit current to groundEither positive or negative output tied to ground20mA
ZDIFFDifferential output impedanceMeasured at DC300Ω
CMOS INTERFACE: SCLK, SDI, SDO, SCS, PD, CALSTAT, CALTRIG, ORA0, ORA1, ORB0, ORB1, SYNCSE
IIHHigh-level input current40µA
IILLow-level input current–40µA
CIInput capacitance2pF
VOHHigh-level output voltageILOAD = –400 µA1.65V
VOLLow-level output voltageILOAD = 400 µA150mV