JAJSFG3C may   2018  – may 2023 ADC12DL3200

PRODUCTION DATA  

  1.   1
  2. 1特長
  3. 2アプリケーション
  4. 3概要
  5. 4Revision History
  6. 5Pin Configuration and Functions
  7. 6Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  8. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Analog Input Protection
        2. 7.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.1.3 Analog Input Offset Adjust
      2. 7.3.2 ADC Core
        1. 7.3.2.1 ADC Theory of Operation
        2. 7.3.2.2 ADC Core Calibration
        3. 7.3.2.3 ADC Overrange Detection
        4. 7.3.2.4 Code Error Rate (CER)
        5. 7.3.2.5 Internal Dither
      3. 7.3.3 Timestamp
      4. 7.3.4 Clocking
        1. 7.3.4.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.4.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.4.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.4.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.4.3.2 Automatic SYSREF Calibration
      5. 7.3.5 LVDS Digital Interface
        1. 7.3.5.1 Multi-Device Synchronization and Deterministic Latency Using Strobes
          1. 7.3.5.1.1 Dedicated Strobe Pins
          2. 7.3.5.1.2 Reduced Width Interface With Dedicated Strobe Pins
          3. 7.3.5.1.3 LSB Replacement With a Strobe
          4. 7.3.5.1.4 Strobe Over All Data Pairs
      6. 7.3.6 Alarm Monitoring
        1. 7.3.6.1 Clock Upset Detection
      7. 7.3.7 Temperature Monitoring Diode
      8. 7.3.8 Analog Reference Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode (Non-DES Mode)
      2. 7.4.2 Internal Dither Modes
      3. 7.4.3 Single-Channel Mode (DES Mode)
      4. 7.4.4 LVDS Output Driver Modes
      5. 7.4.5 LVDS Output Modes
        1. 7.4.5.1 Staggered Output Mode
        2. 7.4.5.2 Aligned Output Mode
        3. 7.4.5.3 Reducing the Number of Strobes
        4. 7.4.5.4 Reducing the Number of Data Clocks
        5. 7.4.5.5 Scrambling
        6. 7.4.5.6 Digital Interface Test Patterns and LVSD SYNC Functionality
          1. 7.4.5.6.1 Active Pattern
          2. 7.4.5.6.2 Synchronization Pattern
          3. 7.4.5.6.3 User-Defined Test Pattern
      6. 7.4.6 Power-Down Modes
      7. 7.4.7 Calibration Modes and Trimming
        1. 7.4.7.1 Foreground Calibration Mode
        2. 7.4.7.2 Background Calibration Mode
        3. 7.4.7.3 Low-Power Background Calibration (LPBG) Mode
      8. 7.4.8 Offset Calibration
      9. 7.4.9 Trimming
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 78
        6. 7.5.1.6 Streaming Mode
        7. 7.5.1.7 80
    6. 7.6 Register Maps
      1. 7.6.1 SPI_REGISTER_MAP Registers
  9.   Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Wideband RF Sampling Receiver
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Input Signal Path
          2. 8.2.1.1.2 Clocking
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Calculating Values of AC-Coupling Capacitors
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Reconfigurable Dual-Channel, 2.5-GSPS or Single-Channel, 5.0-GSPS Oscilloscope
        1. 8.2.2.1 Design Requirements
          1. 8.2.2.1.1 Input Signal Path
          2. 8.2.2.1.2 Clocking
          3. 8.2.2.1.3 The ADC12DL3200
        2. 8.2.2.2 Application Curves
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Sequencing
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 8Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 商標
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  11. 9Mechanical, Packaging, and Orderable Information

7.3.4.1 Noiseless Aperture Delay Adjustment (tAD Adjust)

The ADC12DL3200 contains a delay adjustment on the device clock (sampling clock) input path, called tAD adjust, that can be used to shift the sampling instance within the device in order to align sampling instances among multiple devices or for external interleaving of multiple ADC12DL3200 devices. Further, tAD adjust can be used for automatic SYSREF calibration to simplify synchronization; see the Section 7.3.4.3.2 section. Aperture delay adjustment is implemented in a way that adds no additional noise to the clock path, however a slight degradation in aperture jitter (tAJ) is possible at large values of TAD_COARSE because of internal clock path attenuation. The degradation in aperture jitter can result in minor SNR degradations at high input frequencies (see tAJ in the Section 6.10 table). This feature is programmed using TAD_INV, TAD_COARSE, and TAD_FINE in the DEVCLK timing adjust ramp control register. Setting TAD_INV inverts the input clock resulting in a delay equal to half the clock period. Table 7-4 summarizes the step sizes and ranges of the TAD_COARSE and TAD_FINE variable analog delays. All three delay options are independent and can be used in conjunction. All clocks within the device are shifted by the programmed tAD adjust amount, which results in a shift of the timing of the LVDS data interface and affects the capture of SYSREF.

Table 7-4 tAD Adjust Adjustment Ranges
ADJUSTMENT PARAMETERADJUSTMENT STEPDELAY SETTINGSMAXIMUM DELAY
TAD_INV1 / (fCLK × 2)11 / (fCLK × 2)
TAD_COARSESee tTAD(STEP) in the Section 6.10 table256See tTAD(MAX) in the Section 6.10 table
TAD_FINESee tTAD(STEP) in the Section 6.10 table256See tTAD(MAX) in the Section 6.10 table

In order to maintain timing alignment between converters, stable and matched power-supply voltages and device temperatures must be provided.

Aperture delay adjustment can be changed on-the-fly during normal operation, however changing the aperture delay also shifts the clock for the LVDS data interface (DxCLK±, DxSTR±, and Dx[11:0]±). The receiving circuit must be tolerant of shifts in the LVDS data timing. Use of the TAD_RAMP feature may help the receiver avoid loss of synchronization; see the Section 7.3.4.2 section.