JAJSFG3C may   2018  – may 2023 ADC12DL3200

PRODUCTION DATA  

  1.   1
  2. 1特長
  3. 2アプリケーション
  4. 3概要
  5. 4Revision History
  6. 5Pin Configuration and Functions
  7. 6Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  8. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Analog Input Protection
        2. 7.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.1.3 Analog Input Offset Adjust
      2. 7.3.2 ADC Core
        1. 7.3.2.1 ADC Theory of Operation
        2. 7.3.2.2 ADC Core Calibration
        3. 7.3.2.3 ADC Overrange Detection
        4. 7.3.2.4 Code Error Rate (CER)
        5. 7.3.2.5 Internal Dither
      3. 7.3.3 Timestamp
      4. 7.3.4 Clocking
        1. 7.3.4.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.4.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.4.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.4.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.4.3.2 Automatic SYSREF Calibration
      5. 7.3.5 LVDS Digital Interface
        1. 7.3.5.1 Multi-Device Synchronization and Deterministic Latency Using Strobes
          1. 7.3.5.1.1 Dedicated Strobe Pins
          2. 7.3.5.1.2 Reduced Width Interface With Dedicated Strobe Pins
          3. 7.3.5.1.3 LSB Replacement With a Strobe
          4. 7.3.5.1.4 Strobe Over All Data Pairs
      6. 7.3.6 Alarm Monitoring
        1. 7.3.6.1 Clock Upset Detection
      7. 7.3.7 Temperature Monitoring Diode
      8. 7.3.8 Analog Reference Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode (Non-DES Mode)
      2. 7.4.2 Internal Dither Modes
      3. 7.4.3 Single-Channel Mode (DES Mode)
      4. 7.4.4 LVDS Output Driver Modes
      5. 7.4.5 LVDS Output Modes
        1. 7.4.5.1 Staggered Output Mode
        2. 7.4.5.2 Aligned Output Mode
        3. 7.4.5.3 Reducing the Number of Strobes
        4. 7.4.5.4 Reducing the Number of Data Clocks
        5. 7.4.5.5 Scrambling
        6. 7.4.5.6 Digital Interface Test Patterns and LVSD SYNC Functionality
          1. 7.4.5.6.1 Active Pattern
          2. 7.4.5.6.2 Synchronization Pattern
          3. 7.4.5.6.3 User-Defined Test Pattern
      6. 7.4.6 Power-Down Modes
      7. 7.4.7 Calibration Modes and Trimming
        1. 7.4.7.1 Foreground Calibration Mode
        2. 7.4.7.2 Background Calibration Mode
        3. 7.4.7.3 Low-Power Background Calibration (LPBG) Mode
      8. 7.4.8 Offset Calibration
      9. 7.4.9 Trimming
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 78
        6. 7.5.1.6 Streaming Mode
        7. 7.5.1.7 80
    6. 7.6 Register Maps
      1. 7.6.1 SPI_REGISTER_MAP Registers
  9.   Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Wideband RF Sampling Receiver
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Input Signal Path
          2. 8.2.1.1.2 Clocking
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Calculating Values of AC-Coupling Capacitors
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Reconfigurable Dual-Channel, 2.5-GSPS or Single-Channel, 5.0-GSPS Oscilloscope
        1. 8.2.2.1 Design Requirements
          1. 8.2.2.1.1 Input Signal Path
          2. 8.2.2.1.2 Clocking
          3. 8.2.2.1.3 The ADC12DL3200
        2. 8.2.2.2 Application Curves
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Sequencing
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 8Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 商標
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  11. 9Mechanical, Packaging, and Orderable Information

6.8 Electrical Characteristics: AC Specifications (Single-Channel Mode)

typical values at TA = +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP-DIFF sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in the Recommended Operating Conditions table
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
FPBWFull-power input bandwidth
(–3 dB)(1)		Foreground calibration7.5GHz
Background calibration7.5
CERCode error rateMaximum CER10–18errors/ sample
NSDNoise spectral density, no input signal, excludes fixed interleaving spurs (FS/2 and FS/4 spurs)Maximum full-scale voltage (FS_RANGE_A = 0xFFFF) setting, foreground calibration–154.3dBFS/Hz
Default full-scale voltage (FS_RANGE_A = 0xA000) setting, foreground calibration–152.5
NFNoise figureMaximum full-scale voltage (FS_RANGE_A = 0xFFFF) setting, foreground calibration, no input, ZS = 100 Ω18.7dB
Default full-scale voltage (FS_RANGE_A = 0xA000) setting, foreground calibration, no input, ZS = 100 Ω20.5
NOISEDCDC input noise standard deviationNo input, foreground calibration, excludes DC offset, includes fixed interleaving spurs (FS/2 and FS/4 spurs)3.1LSB
SNRSignal-to-noise ratio, large signal, excluding DC, HD2 to HD9 and interleaving spursfIN = 347 MHz, AIN = –1 dBFS57.0dBFS
fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration57.9
fIN = 997 MHz, AIN = –1 dBFS56.8
fIN = 2482 MHz, AIN = –1 dBFS5255.8
fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration56.5
fIN = 4997 MHz, AIN = –1 dBFS53.2
fIN = 6397 MHz, AIN = –1 dBFS51.4
fIN = 8197 MHz, AIN = –1 dBFS50.1
SNRSignal-to-noise ratio, small signal, excluding DC, HD2 to HD9 and interleaving spursfIN = 347 MHz, AIN = –16 dBFS57.8dBFS
fIN = 997 MHz, AIN = –16 dBFS57.7
fIN = 2482 MHz, AIN = –16 dBFS57.8
fIN = 4997 MHz, AIN = –16 dBFS57.5
fIN = 6397 MHz, AIN = –16 dBFS57.1
fIN = 8197 MHz, AIN = –16 dBFS57.1
SINADSignal-to-noise and distortion ratio, large signal, excluding DC and FS/2 fixed spursfIN = 347 MHz, AIN = –1 dBFS55.9dBFS
fIN = 997 MHz, AIN = –1 dBFS54.0
fIN = 2482 MHz, AIN = –1 dBFS4853.3
fIN = 4997 MHz, AIN = –1 dBFS50.5
fIN = 6397 MHz, AIN = –1 dBFS48.5
fIN = 8197 MHz, AIN = –1 dBFS44.0
ENOBEffective number of bits, large signal, excluding DC and FS/2 fixed spursfIN = 347 MHz, AIN = –1 dBFS9.0Bits
fIN = 997 MHz, AIN = –1 dBFS8.7
fIN = 2482 MHz, AIN = –1 dBFS7.78.6
fIN = 4997 MHz, AIN = –1 dBFS8.1
fIN = 6397 MHz, AIN = –1 dBFS7.8
fIN = 8197 MHz, AIN = –1 dBFS7.0
SFDRSpurious-free dynamic range, large signal, excluding DC, FS/4 and FS/2 fixed spursfIN = 347 MHz, AIN = –1 dBFS67dBFS
fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration66
fIN = 997 MHz, AIN = –1 dBFS62
fIN = 2482 MHz, AIN = –1 dBFS5061
fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration58
fIN = 4997 MHz, AIN = –1 dBFS58
fIN = 6397 MHz, AIN = –1 dBFS56
fIN = 8197 MHz, AIN = –1 dBFS47
SFDRSpurious-free dynamic range, small signal, excluding DC, FS/4 and FS/2 fixed spursfIN = 347 MHz, AIN = –16 dBFS78dBFS
fIN = 997 MHz, AIN = –16 dBFS76
fIN = 2482 MHz, AIN = –16 dBFS73
fIN = 4997 MHz, AIN = –16 dBFS76
fIN = 6397 MHz, AIN = –16 dBFS70
fIN = 8197 MHz, AIN = –16 dBFS62
FS/2FS/2 fixed interleaving spur, independent of input signalNo input–62dBFS
FS/4FS/4 fixed interleaving spur, independent of input signalNo input–69–55dBFS
HD22nd-order harmonicfIN = 347 MHz, AIN = –1 dBFS–75dBFS
fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration–73
fIN = 997 MHz, AIN = –1 dBFS–68
fIN = 2482 MHz, AIN = –1 dBFS–66–56
fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration–64
fIN = 4997 MHz, AIN = –1 dBFS–69
fIN = 6397 MHz, AIN = –1 dBFS–64
fIN = 8197 MHz, AIN = –1 dBFS–68
HD33rd-order harmonicfIN = 347 MHz, AIN = –1 dBFS–74dBFS
fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration–72
fIN = 997 MHz, AIN = –1 dBFS–66
fIN = 2482 MHz, AIN = –1 dBFS–66–56
fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration–61
fIN = 4997 MHz, AIN = –1 dBFS–59
fIN = 6397 MHz, AIN = –1 dBFS–59
fIN = 8197 MHz, AIN = –1 dBFS–56
FS/2-FINFS/2-FIN interleaving spur, signal dependentfIN = 347 MHz, AIN = –1 dBFS–68dBFS
fIN = 997 MHz, AIN = –1 dBFS–63
fIN = 2482 MHz, AIN = –1 dBFS–62–50
fIN = 4997 MHz, AIN = –1 dBFS–62
fIN = 6397 MHz, AIN = –1 dBFS–56
fIN = 8197 MHz, AIN = –1 dBFS–47
FS/4±FINFS/4±FIN interleaving spurs, signal dependentfIN = 347 MHz, AIN = –1 dBFS–75dBFS
fIN = 997 MHz, AIN = –1 dBFS–71
fIN = 2482 MHz, AIN = –1 dBFS–77–60
fIN = 4997 MHz, AIN = –1 dBFS–74
fIN = 6397 MHz, AIN = –1 dBFS–70
fIN = 8197 MHz, AIN = –1 dBFS–68
SPURWorst harmonic 4th-order or higherfIN = 347 MHz, AIN = –1 dBFS–73dBFS
fIN = 997 MHz, AIN = –1 dBFS–73
fIN = 2482 MHz, AIN = –1 dBFS–75–60
fIN = 4997 MHz, AIN = –1 dBFS–74
fIN = 6397 MHz, AIN = –1 dBFS–69
fIN = 8197 MHz, AIN = –1 dBFS–68
IMD33rd-order intermodulationfIN = 347 MHz ± 5 MHz,
AIN = –7 dBFS per tone		–81dBFS
fIN = 997 MHz ± 5 MHz,
AIN = –7 dBFS per tone		–80
fIN = 2482 MHz ± 5 MHz,
AIN = –7 dBFS per tone		–72
fIN = 4997 MHz ± 5 MHz,
AIN = –7 dBFS per tone		–62
fIN = 6397 MHz ± 5 MHz,
AIN = –7 dBFS per tone		–56
fIN = 8197 MHz ± 5 MHz,
AIN = –7 dBFS per tone		–49
(1) Full-power input bandwidth (FPBW) is defined as the input frequency where the reconstructed output of the ADC has dropped 3 dB below the power of a full-scale input signal at a low input frequency. Useable bandwidth may exceed the –3-dB full-power input bandwidth.