JAJSFI2D May   2018  – May 2022 AMC1300

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics
    10. 7.10 Switching Characteristics
    11. 7.11 Timing Diagram
    12. 7.12 Insulation Characteristics Curves
    13. 7.13 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
      2. 8.3.2 Isolation Channel Signal Transmission
      3. 8.3.3 Analog Output
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Shunt Resistor Sizing
        2. 9.2.2.2 Input Filter Design
        3. 9.2.2.3 Differential-to-Single-Ended Output Conversion
      3. 9.2.3 Application Curves
    3. 9.3 What To Do and What Not To Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

7.6 Insulation Specifications

over operating ambient temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VALUE UNIT
GENERAL
CLR External clearance(1) Shortest terminal-to-terminal distance through air ≥ 8.5 mm
CPG External Creepage(1) Shortest terminal-to-terminal distance across the package surface ≥ 8.5 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) of the double isolation (2 x 0.0105 mm) ≥ 0.021 mm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 ≥ 600 V
Material Group According to IEC 60664-1 I
Overvoltage category Rated mains voltage ≤ 600 VRMS I-IV
Rated mains voltage ≤ 1000 VRMS I-III
DIN VDE 0884-11 (VDE V 0884-11): 2017-01
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 2121 VPK
VIOWM Maximum isolation working voltage AC voltage (sine wave); time-dependent dielectric breakdown (TDDB) test; see Figure 4 1500 VRMS
DC voltage 2121 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60 s (qualification test) 7071 VPK
VTEST = VIOTM, t = 1 s (100% production test) 8485 VPK
VIOSM Maximum surge isolation voltage(2) Test method per IEC 60065, 1.2/50 µs waveform, VTEST = 1.6 × VIOSM = 12800 VPK (qualification) 8000 VPK
qpd Apparent charge(3) Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM = 2545 VPK, tm = 10 s ≤ 5 pC
Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM = 3394 VPK, tm = 10 s ≤ 5
Method b1: At routine test (100% production) and preconditioning (type test), Vini = VIOTM, tini = 1 s; Vpd(m) = 1.875 × VIORM = 3977 VPK, tm = 1 s ≤ 5
CIO Barrier capacitance, input to output(4) VIO = 0.4 × sin (2 πft), f = 1 MHz ~1.5 pF
RIO Insulation resistance, input to output(4) VIO = 500 V,  TA = 25°C > 1012 Ω
VIO = 500 V,  100°C ≤ TA ≤ 125°C > 1011
VIO = 500 V at  TS = 150°C > 109
Pollution degree 2
Climatic category 55/125/21
UL 1577
VISO Withstand isolation voltage VTEST = VISO = 5000 VRMS, t = 60 s (qualification), VTEST = 1.2 × VISO = 6000 VRMS, t = 1 s (100% production) 5000 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Careshould be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator onthe printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.Techniques such as inserting grooves, ribs, or both on a printed-circuit board are used to help increase these specifications.
(2) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(3) Apparent charge is electrical discharge caused by a partial discharge (pd).
(4) All pins on each side of the barrier tied together creating a two-pin device.