8.6 Register Maps
The LMH1218 register set definition is divided into four groups:
- Global Registers: Chip ID, Interrupt status, LOS registers
- Receiver Registers: Equalizer boost settings and signal detect setting
- CDR Registers: PLL control
- Transmitter Registers: OUT0 and OUT1 parameter setting
Additionally, the global register is divided into share and channel registers. Share registers define chip ID, device revision while channel registers are feature-specific.
The typical device initialization sequence for the LMH1218 includes the followings. For detailed register settings refer to LMH1218 Programming Guide (SNLU174).
- Shared Register Configuration
- Reading device ID
- Selecting interrupt on to LOS pin
- Settings up the register to access the channel registers
- Channel Register Configuration
- CDR Reset
- Interrupt register configuration
- CDR data rate selection
- Optional Input/Output selection
- Optional VOD selection
- CDR Reset and Release