JAJSFM3E February 2015 – June 2018 LMH1218
PRODUCTION DATA.
REGISTER NAME | BITS | FIELD REGISTER ADDRESS | DEFAULT | R/RW | DESCRIPTION |
---|---|---|---|---|---|
EQ_Boost | Reg 0x03 Channel | 0x80 | 4 Stage EQ Boost Levels. Read-back value going to CTLE in reg_0x52. Used for setting EQ value when reg_0x2D[3] is high | ||
7 | eq_BST0[1] | 1 | RW | 2 Bits control for stage 0 of the CTLE. Adapts during CTLE adaptation | |
6 | eq_BST0[0] | 0 | RW | ||
5 | eq_BST1[1] | 0 | RW | 2 Bits control for stage 1 of the CTLE. Adapts during CTLE adaptation | |
4 | eq_BST1[0] | 0 | RW | ||
3 | eq_BST2[1] | 0 | RW | 2 Bits control for stage 2 of the CTLE. Adapts during CTLE adaptation | |
2 | eq_BST2[0] | 0 | RW | ||
1 | eq_BST3[1] | 0 | RW | 2 Bits control for stage 3 of the CTLE. Adapts during CTLE adaptation | |
0 | eq_BST3[0] | 0 | RW | ||
SD_EQ | Reg_0x0D Channel | 0x00 | 270 Mbps EQ Boost Setting | ||
7 | Reserved | 0 | RW | ||
6 | Reserved | 0 | RW | ||
5 | Reserved | 0 | RW | ||
4 | Reserved | 0 | RW | ||
3 | Reserved | 0 | RW | ||
2 | Reserved | 0 | RW | ||
1 | Reserved | 0 | RW | ||
0 | Mr_auto_eq_en_bypass | 0 | RW | 1: EQ Bypass for 270 Mbps
0: Use EQ Settings in reg0x03[7:0] for 270 Mbps Note: If 0x13[1] mr_eq_en_bypass is set, bypass would be set and auto-bypass has no significance. |
|
EQ_SD_CONFIG | Reg 0x13 Channel | 0x90 | Channel EQ Bypass and Power Down | ||
7 | Reserved | 1 | RW | ||
6 | sd_0_PD | 0 | RW | 1: Power Down IN0 Signal Detect
0: IN0 Signal Detect normal operation |
|
5 | sd_1_PD | 0 | RW | 1: Power Down IN1 Signal Detect
0: IN1 Signal Detect normal operation |
|
4 | Reserved | 1 | RW | ||
3 | eq_PD_EQ | 0 | RW | Controls the power-state of the selected channel. The un-selected channel is always powered-down
1: Powers down selected channel EQ stage 0: Powers up EQ of the selected channel |
|
2 | Reserved | 0 | RW | ||
1 | eq_en_bypass | 0 | RW | 1: Bypass stage 3 and 4 of CTLE
0: Enable Stage 3 and 4 of CTLE |
|
0 | Reserved | 0 | RW | ||
SD0_CONFIG | Reg 0x14 Channel | 0x00 | IN0 Signal Detect Threshold Setting | ||
7 | Reserved | 0 | RW | ||
6 | Reserved | 0 | RW | ||
5 | sd_0_refa_sel[1] | 0 | RW | Controls signal detect SDH- Assert [5:4], SDL- De-Assert [3:2], thresholds for IN0
0000: Default levels (nominal) 0101: Nominal -2 mV 1010: Nominal +5 mV 1111: Nominal +3 mV |
|
4 | sd_0_refa_sel[0] | 0 | RW | ||
3 | sd_0_refd_sel[1] | 0 | RW | ||
2 | sd_0_refd_sel[0] | 0 | RW | ||
1 | Reserved | 0 | RW | ||
0 | Reserved | 0 | RW | ||
SD1_CONFIG | Reg_0x15 Channel | 0x00 | IN1 Signal Detect Threshold Setting | ||
7 | Reserved | 0 | RW | ||
6 | Reserved | 0 | RW | ||
5 | sd_1_refa_sel[1] | 0 | RW | Controls signal detect SDH- Assert [5:4], SDL- De-Assert [3:2], thresholds for IN1
0000: Default levels (nominal) 0101: Nominal -2 mV 1010: Nominal +5 mV 1111: Nominal +3 mV |
|
4 | sd_1_refa_sel[0] | 0 | RW | ||
3 | sd_1_refd_sel[1] | 0 | RW | ||
2 | sd_1_refd_sel[0] | 0 | RW | ||
1 | Reserved | 0 | RW | ||
0 | Reserved | 0 | RW | ||
EQ_BOOST_OV | Reg_0x2D Channel | 0x88 | EQ Boost Override | ||
7 | Reserved | 1 | RW | ||
6 | Reserved | 0 | RW | ||
5 | Reserved | 0 | RW | ||
4 | Reserved | 0 | RW | ||
3 | reg_eq_bst_ov | 1 | RW | 1: Enable EQ boost over ride- refer to theLMH1218 Programming Guide (SNLU174)
0: Disable EQ boost over ride |
|
2 | Reserved | 0 | RW | ||
1 | Reserved | 0 | RW | ||
0 | Reserved | 0 | RW | ||
CTLE Setting | Reg_0x31 Channel | 0x00 | CTLE Mode of Operation and Input/Output Mux Selection | ||
7 | Reserved | 0 | RW | ||
6 | adapt_mode[1] | 00 | RW | 00: Normal Operation - Manual CTLE Setting
01: Test Mode - Refer to the LMH1218 Programming Guide (SNLU174) Other Settings - Invalid |
|
5 | adapt_mode[0] | ||||
4 | Reserved | 0 | RW | ||
3 | Reserved | 0 | RW | ||
2 | Reserved | 0 | RW | ||
1 | input_mux_ch_sel[1] | 0 | RW | IN0/1 and OUT0/1 selection
00: selects IN0 and OUT0/1 01: selects IN0 and OUT0 10: selects IN1 and OUT1 11: selects IN1 and OUT0/1 |
|
0 | input_mux_ch_sel[0] | 0 | RW | ||
LOW_RATE_
EQ_BST |
Reg 0x3A Channel | 0x00 | HD and SD EQ Level | ||
7 | fixed_eq_BST0[1] | 0 | RW | When CTLE is operating in test mode, Reg 0x3A[7:0] forces fixed EQ setting for data rates <= 3Gbps. In normal operating manual mode Reg_0x03 forces EQ boost. Note LMH1218 Programming Guide (SNLU174) for details | |
6 | fixed_eq_BST0[0] | 0 | RW | ||
5 | fixed_eq_BST1[1] | 0 | RW | ||
4 | fixed_eq_BST1[0] | 0 | RW | ||
3 | fixed_eq_BST2[1] | 0 | RW | ||
2 | fixed_eq_BST2[0] | 0 | RW | ||
1 | fixed_eq_BST3[1] | 0 | RW | ||
0 | fixed_eq_BST3[0] | 0 | RW | ||
BST_Indx0 | Reg_0x40 Channel | 0x00 | Index0 4 Stage EQ Boost. Note LMH1218 Programming Guide (SNLU174) for details | ||
7 | I0_BST0[1] | 0 | RW | Index 0 Boost Stage 0 bit 1 | |
6 | I0_BST0[0] | 0 | RW | Index 0 Boost Stage 0 bit 0 | |
5 | I0_BST1[1] | 0 | RW | Index 0 Boost Stage 1 bit 1 | |
4 | I0_BST1[0] | 0 | RW | Index 0 Boost Stage 1 bit 0 | |
3 | I0_BST2[1] | 0 | RW | Index 0 Boost Stage 2 bit 1 | |
2 | I0_BST2[0] | 0 | RW | Index 0 Boost Stage 2 bit 0 | |
1 | I0_BST3[1] | 0 | RW | Index 0 Boost Stage 3 bit 1 | |
0 | I0_BST3[0] | 0 | RW | Index 0 Boost Stage 3 bit 0 | |
BST_Indx1 | Reg 0x41 Channel | 0x40 | Index1 4 Stage EQ Boost. | ||
7 | I1_BST0[1] | 0 | RW | Index 1 Boost Stage 0 bit 1 | |
6 | I1_BST0[0] | 1 | RW | Index 1 Boost Stage 0 bit 0 | |
5 | I1_BST1[1] | 0 | RW | Index 1 Boost Stage 1 bit 1 | |
4 | I1_BST1[0] | 0 | RW | Index 1 Boost Stage 1 bit 0 | |
3 | I1_BST2[1] | 0 | RW | Index 1 Boost Stage 2 bit 1 | |
2 | I1_BST2[0] | 0 | RW | Index 1 Boost Stage 2 bit 0 | |
1 | I1_BST3[1] | 0 | RW | Index 1 Boost Stage 3 bit 1 | |
0 | I1_BST3[0] | 0 | RW | Index 1 Boost Stage 3 bit 0 | |
BST_Indx2 | Reg 0x42 Channel | 0x80 | Index2 4 Stage EQ Boost. | ||
7 | I2_BST0[1] | 1 | RW | Index 2 Boost Stage 0 bit 1 | |
6 | I2_BST0[0] | 0 | RW | Index 2 Boost Stage 0 bit 0 | |
5 | I2_BST1[1] | 0 | RW | Index 2 Boost Stage 1 bit 1 | |
4 | I2_BST1[0] | 0 | RW | Index 2 Boost Stage 1 bit 0 | |
3 | I2_BST2[1] | 0 | RW | Index 2 Boost Stage 2 bit 1 | |
2 | I2_BST2[0] | 0 | RW | Index 2 Boost Stage 2 bit 0 | |
1 | I2_BST3[1] | 0 | RW | Index 2 Boost Stage 3 bit 1 | |
0 | I2_BST3[0] | 0 | RW | Index 2 Boost Stage 3 bit 0 | |
BST_Indx3 | Reg 0x43 Channel | 0x50 | Index3 4 Stage EQ Boost. | ||
7 | I3_BST0[1] | 0 | RW | Index 3 Boost Stage 0 bit 1 | |
6 | I3_BST0[0] | 1 | RW | Index 3 Boost Stage 0 bit 0 | |
5 | I3_BST1[1] | 0 | RW | Index 3 Boost Stage 1 bit 1 | |
4 | I3_BST1[0] | 1 | RW | Index 3 Boost Stage 1 bit 0 | |
3 | I3_BST2[1] | 0 | RW | Index 3 Boost Stage 2 bit 1 | |
2 | I3_BST2[0] | 0 | RW | Index 3 Boost Stage 2 bit 0 | |
1 | I3_BST3[1] | 0 | RW | Index 3 Boost Stage 3 bit 1 | |
0 | I3_BST3[0] | 0 | RW | Index 3 Boost Stage 3 bit 0 | |
BST_Indx4 | Reg 0x44 Channel | 0xC0 | Index4 4 Stage EQ Boost. | ||
7 | I4_BST0[1] | 1 | RW | Index 4 Boost Stage 0 bit 1 | |
6 | I4_BST0[0] | 1 | RW | Index 4 Boost Stage 0 bit 0 | |
5 | I4_BST1[1] | 0 | RW | Index 4 Boost Stage 1 bit 1 | |
4 | I4_BST1[0] | 0 | RW | Index 4 Boost Stage 1 bit 0 | |
3 | I4_BST2[1] | 0 | RW | Index 4 Boost Stage 2 bit 1 | |
2 | I4_BST2[0] | 0 | RW | Index 4 Boost Stage 2 bit 0 | |
1 | I4_BST3[1] | 0 | RW | Index 4 Boost Stage 3 bit 1 | |
0 | I4_BST3[0] | 0 | RW | Index 4 Boost Stage 3 bit 0 | |
BST_Indx5 | Reg 0x45 Channel | 0x90 | Index5 4 Stage EQ Boost. | ||
7 | I5_BST0[1] | 1 | RW | Index 5 Boost Stage 0 bit 1 | |
6 | I5_BST0[0] | 0 | RW | Index 5 Boost Stage 0 bit 0 | |
5 | I5_BST1[1] | 0 | RW | Index 5 Boost Stage 1 bit 1 | |
4 | I5_BST1[0] | 1 | RW | Index 5 Boost Stage 1 bit 0 | |
3 | I5_BST2[1] | 0 | RW | Index 5 Boost Stage 2 bit 1 | |
2 | I5_BST2[0] | 0 | RW | Index 5 Boost Stage 2 bit 0 | |
1 | I5_BST3[1] | 0 | RW | Index 5 Boost Stage 3 bit 1 | |
0 | I5_BST3[0] | 0 | RW | Index 5 Boost Stage 3 bit 0 | |
BST_Indx6 | Reg 0x46 Channel | 0x54 | Index6 4 Stage EQ Boost. | ||
7 | I6_BST0[1] | 0 | RW | Index 6 Boost Stage 0 bit 1 | |
6 | I6_BST0[0] | 1 | RW | Index 6 Boost Stage 0 bit 0 | |
5 | I6_BST1[1] | 0 | RW | Index 6 Boost Stage 1 bit 1 | |
4 | I6_BST1[0] | 1 | RW | Index 6 Boost Stage 1 bit 0 | |
3 | I6_BST2[1] | 0 | RW | Index 6 Boost Stage 2 bit 1 | |
2 | I6_BST2[0] | 1 | RW | Index 6 Boost Stage 2 bit 0 | |
1 | I6_BST3[1] | 0 | RW | Index 6 Boost Stage 3 bit 1 | |
0 | I6_BST3[0] | 0 | RW | Index 6 Boost Stage 3 bit 0 | |
BST_Indx7 | Reg 0x47 Channel | 0xA0 | Index7 4 Stage EQ Boost. | ||
7 | I7_BST0[1] | 1 | RW | Index 7 Boost Stage 0 bit 1 | |
6 | I7_BST0[0] | 0 | RW | Index 7 Boost Stage 0 bit 0 | |
5 | I7_BST1[1] | 1 | RW | Index 7 Boost Stage 1 bit 1 | |
4 | I7_BST1[0] | 0 | RW | Index 7 Boost Stage 1 bit 0 | |
3 | I7_BST2[1] | 0 | RW | Index 7 Boost Stage 2 bit 1 | |
2 | I7_BST2[0] | 0 | RW | Index 7 Boost Stage 2 bit 0 | |
1 | I7_BST3[1] | 0 | RW | Index 7 Boost Stage 3 bit 1 | |
0 | I7_BST3[0] | 0 | RW | Index 7 Boost Stage 3 bit 0 | |
BST_Indx8 | Reg 0x48 Channel | 0xB0 | Index8 4 Stage EQ Boost. | ||
7 | I8_BST0[1] | 1 | RW | Index 8 Boost Stage 0 bit 1 | |
6 | I8_BST0[0] | 0 | RW | Index 8 Boost Stage 0 bit 0 | |
5 | I8_BST1[1] | 1 | RW | Index 8 Boost Stage 1 bit 1 | |
4 | I8_BST1[0] | 1 | RW | Index 8 Boost Stage 1 bit 0 | |
3 | I8_BST2[1] | 0 | RW | Index 8 Boost Stage 2 bit 1 | |
2 | I8_BST2[0] | 0 | RW | Index 8 Boost Stage 2 bit 0 | |
1 | I8_BST3[1] | 0 | RW | Index 8 Boost Stage 3 bit 1 | |
0 | I8_BST3[0] | 0 | RW | Index 8 Boost Stage 3 bit 0 | |
BST_Indx9 | Reg 0x49 Channel | 0X95 | 0x95 | Index9 4 Stage EQ Boost. | |
7 | I9_BST0[1] | 1 | RW | Index 9 Boost Stage 0 bit 1 | |
6 | I9_BST0[0] | 0 | RW | Index 9 Boost Stage 0 bit 0 | |
5 | I9_BST1[1] | 0 | RW | Index 9 Boost Stage 1 bit 1 | |
4 | I9_BST1[0] | 1 | RW | Index 9 Boost Stage 1 bit 0 | |
3 | I9_BST2[1] | 0 | RW | Index 9 Boost Stage 2 bit 1 | |
2 | I9_BST2[0] | 1 | RW | Index 9 Boost Stage 2 bit 0 | |
1 | I9_BST3[1] | 0 | RW | Index 9 Boost Stage 3 bit 1 | |
0 | I9_BST3[0] | 1 | RW | Index 9 Boost Stage 3 bit 0 | |
BST_Indx10 | Reg 0x4A Channel | 0x69 | Index10 4 Stage EQ Boost. | ||
7 | I10_BST0[1] | 0 | RW | Index 10 Boost Stage 0 bit 1 | |
6 | I10_BST0[0] | 1 | RW | Index 10 Boost Stage 0 bit 0 | |
5 | I10_BST1[1] | 1 | RW | Index 10 Boost Stage 1 bit 1 | |
4 | I10_BST1[0] | 0 | RW | Index 10 Boost Stage 1 bit 0 | |
3 | I10_BST2[1] | 1 | RW | Index 10 Boost Stage 2 bit 1 | |
2 | I10_BST2[0] | 0 | RW | Index 10 Boost Stage 2 bit 0 | |
1 | I10_BST3[1] | 0 | RW | Index 10 Boost Stage 3 bit 1 | |
0 | I10_BST3[0] | 1 | RW | Index 10 Boost Stage 3 bit 0 | |
BST_Indx11 | Reg 0x4B Channel | 0xD5 | Index11 4 Stage EQ Boost. | ||
7 | I11_BST0[1] | 1 | RW | Index 11 Boost Stage 0 bit 1 | |
6 | I11_BST0[0] | 1 | RW | Index 11 Boost Stage 0 bit 0 | |
5 | I11_BST1[1] | 0 | RW | Index 11 Boost Stage 1 bit 1 | |
4 | I11_BST1[0] | 1 | RW | Index 11 Boost Stage 1 bit 0 | |
3 | I11_BST2[1] | 0 | RW | Index 11 Boost Stage 2 bit 1 | |
2 | I11_BST2[0] | 1 | RW | Index 11 Boost Stage 2 bit 0 | |
1 | I11_BST3[1] | 0 | RW | Index 11 Boost Stage 3 bit 1 | |
0 | I11_BST3[0] | 1 | RW | Index 11 Boost Stage 3 bit 0 | |
BSTIndx12 | Reg 0x4C Channel | 0x99 | Index12 4 Stage EQ Boost. | ||
7 | I12_BST0[1] | 1 | RW | Index 12 Boost Stage 0 bit 1 | |
6 | I12_BST0[0] | 0 | RW | Index 12 Boost Stage 0 bit 0 | |
5 | I12_BST1[1] | 0 | RW | Index 12 Boost Stage 1 bit 1 | |
4 | I12_BST1[0] | 1 | RW | Index 12 Boost Stage 1 bit 0 | |
3 | I12_BST2[1] | 1 | RW | Index 12 Boost Stage 2 bit 1 | |
2 | I12_BST2[0] | 0 | RW | Index 12 Boost Stage 2 bit 0 | |
1 | I12_BST3[1] | 0 | RW | Index 12 Boost Stage 3 bit 1 | |
0 | I12_BST3[0] | 1 | RW | Index 12 Boost Stage 3 bit 0 | |
BST_Indx13 | Reg 0x4D Channel | 0xA5 | Index13 4 Stage EQ Boost. | ||
7 | I13_BST0[1] | 1 | RW | Index 13 Boost Stage 0 bit 1 | |
6 | I13_BST0[0] | 0 | RW | Index 13 Boost Stage 0 bit 0 | |
5 | I13_BST1[1] | 1 | RW | Index 13 Boost Stage 1 bit 1 | |
4 | I13_BST1[0] | 0 | RW | Index 13 Boost Stage 1 bit 0 | |
3 | I13_BST2[1] | 0 | RW | Index 13 Boost Stage 2 bit 1 | |
2 | I13_BST2[0] | 1 | RW | Index 13 Boost Stage 2 bit 0 | |
1 | I13_BST3[1] | 0 | RW | Index 13 Boost Stage 3 bit 1 | |
0 | I13_BST3[0] | 1 | RW | Index 13 Boost Stage 3 bit 0 | |
BST_Indx14 | Reg 0x4E Channel | 0xE6 | Index14 4 Stage EQ Boost. | ||
7 | I14_BST0[1] | 1 | RW | Index 14 Boost Stage 0 bit 1 | |
6 | I14_BST0[0] | 1 | RW | Index 14 Boost Stage 0 bit 0 | |
5 | I14_BST1[1] | 1 | RW | Index 14 Boost Stage 1 bit 1 | |
4 | I14_BST1[0] | 0 | RW | Index 14 Boost Stage 1 bit 0 | |
3 | I14_BST2[1] | 0 | RW | Index 14 Boost Stage 2 bit 1 | |
2 | I14_BST2[0] | 1 | RW | Index 14 Boost Stage 2 bit 0 | |
1 | I14_BST3[1] | 1 | RW | Index 14 Boost Stage 3 bit 1 | |
0 | I14_BST3[0] | 0 | RW | Index 14 Boost Stage 3 bit 0 | |
BST_Indx15 | Reg 0x4F Channel | 0xF9 | Index15 4 Stage EQ Boost. | ||
7 | I15_BST0[1] | 1 | RW | Index 15 Boost Stage 0 bit 1 | |
6 | I15_BST0[0] | 1 | RW | Index 15 Boost Stage 0 bit 0 | |
5 | I15_BST1[1] | 1 | RW | Index 15 Boost Stage 1 bit 1 | |
4 | I15_BST1[0] | 1 | RW | Index 15 Boost Stage 1 bit 0 | |
3 | I15_BST2[1] | 1 | RW | Index 15 Boost Stage 2 bit 1 | |
2 | I15_BST2[0] | 0 | RW | Index 15 Boost Stage 2 bit 0 | |
1 | I15_BST3[1] | 0 | RW | Index 15 Boost Stage 3 bit 1 | |
0 | I15_BST3[0] | 1 | RW | Index 15 Boost Stage 3 bit 0 | |
Active_EQ | Reg 0x52 Channel | 0x00 | Active CTLE Boost Setting Read Back | ||
7 | eq_bst_to_ana[7] | 0 | R | Read-back returns CTLE boost settings | |
6 | eq_bst_to_ana[6] | 0 | R | ||
5 | eq_bst_to_ana[5] | 0 | R | ||
4 | eq_bst_to_ana[4] | 0 | R | ||
3 | eq_bst_to_ana[3] | 0 | R | ||
2 | eq_bst_to_ana[2] | 0 | R | ||
1 | eq_bst_to_ana[1] | 0 | R | ||
0 | eq_bst_to_ana[0] | 0 | R | ||
EQ_Control | Reg 0x55 Channel | 0x00 | Low Rate <=3G EQ Adaptation Control | ||
7 | Reserved | 0 | R | ||
6 | Reserved | 0 | RW | ||
5 | Reserved | 0 | RW | ||
4 | Reserved | 0 | RW | ||
3 | Reserved | 0 | RW | ||
2 | Reserved | 0 | RW | ||
1 | Reserved | 0 | RW | At power-up, this bit needs to be set to 1'b. See initialization set up | |
0 | Reserved | 0 | RW |