JAJSFO7D March   2008  – November 2023 UCC27324-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Overall Electrical Characteristics
    6. 5.6  Power Dissipation Characteristics
    7. 5.7  Input (INA, INB) Electrical Characteristics
    8. 5.8  Output (OUTA, OUTB) Electrical Characteristics
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Stage
      2. 6.3.2 Output Stage
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Parallel Outputs
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Propagation Delay
        2. 7.2.2.2 Source and Sink Capabilities During Miller Plateau
        3. 7.2.2.3 Supply Voltage (VDD)
        4. 7.2.2.4 Drive Current and Power Requirements
      3. 7.2.3 Application Curve
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 サード・パーティ製品に関する免責事項
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.2.2.3 Supply Voltage (VDD)

Although quiescent VDD current is very low, total supply current is higher, depending on the OUTA and OUTB current and the programmed oscillator frequency. The total VDD current is the sum of quiescent VDD current and the average OUT current. With the known operating frequency and the MOSFET gate charge (Qg), use Equation 1 to calculate the average OUT current.

Equation 1. IOUT = Qg × f

where

  • f is frequency

For the best high-speed circuit performance, two VDD bypass capacitors are recommended to prevent noise problems. The use of surface mount components is highly recommended. A 0.1-μF ceramic capacitor must be located closest to the VDD to ground connection. In addition, a larger capacitor (such as 1-μF) with relatively low ESR must be connected in parallel, to help deliver the high current peaks to the load. The parallel combination of capacitors must present a low impedance characteristic for the expected current levels in the driver application