JAJSFR6A July   2018  – November 2018 ADS1219

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      電圧、電流、および温度監視アプリケーション
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Timing Requirements
    7. 7.7 I2C Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Multiplexer
      2. 9.3.2 Rail-to-Rail Input Buffers and Programmable Gain Stage
      3. 9.3.3 Voltage Reference
      4. 9.3.4 Modulator and Internal Oscillator
      5. 9.3.5 Digital Filter
      6. 9.3.6 Conversion Times
      7. 9.3.7 Offset Calibration
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Up and Reset
        1. 9.4.1.1 Power-On Reset
        2. 9.4.1.2 RESET Pin
        3. 9.4.1.3 Reset by Command
      2. 9.4.2 Conversion Modes
        1. 9.4.2.1 Single-Shot Conversion Mode
        2. 9.4.2.2 Continuous Conversion Mode
      3. 9.4.3 Power-Down Mode
    5. 9.5 Programming
      1. 9.5.1 I2C Interface
        1. 9.5.1.1 I2C Address
        2. 9.5.1.2 Serial Clock (SCL) and Serial Data (SDA)
        3. 9.5.1.3 Data Ready (DRDY)
        4. 9.5.1.4 Interface Speed
        5. 9.5.1.5 Data Transfer Protocol
        6. 9.5.1.6 I2C General Call (Software Reset)
        7. 9.5.1.7 Timeout
      2. 9.5.2 Data Format
      3. 9.5.3 Commands
        1. 9.5.3.1 Command Latching
        2. 9.5.3.2 RESET (0000 011x)
        3. 9.5.3.3 START/SYNC (0000 100x)
        4. 9.5.3.4 POWERDOWN (0000 001x)
        5. 9.5.3.5 RDATA (0001 xxxx)
        6. 9.5.3.6 RREG (0010 0rxx)
        7. 9.5.3.7 WREG (0100 00xx dddd dddd)
      4. 9.5.4 Reading Data and Monitoring for New Conversion Results
    6. 9.6 Register Map
      1. 9.6.1 Configuration and Status Registers
      2. 9.6.2 Register Descriptions
        1. 9.6.2.1 Configuration Register (address = 0h) [reset = 00h]
          1. Table 10. Configuration Register Field Descriptions
        2. 9.6.2.2 Status Register (address = 1h) [reset = 00h]
          1. Table 11. Status Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Interface Connections
      2. 10.1.2 Connecting Multiple Devices on the Same I2C Bus
      3. 10.1.3 Unused Inputs and Outputs
      4. 10.1.4 Analog Input Filtering
      5. 10.1.5 External Reference and Ratiometric Measurements
      6. 10.1.6 Establishing Proper Limits on the Absolute Input Voltage
      7. 10.1.7 Pseudo Code Example
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Voltage Monitoring
        2. 10.2.2.2 High-Side Current Measurement
        3. 10.2.2.3 Thermistor Measurement
        4. 10.2.2.4 Register Settings
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Sequencing
    2. 11.2 Power-Supply Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

9.3.2 Rail-to-Rail Input Buffers and Programmable Gain Stage

The ADS1219 integrates two rail-to-rail input buffers to ensure that the effect on the input loading resulting from the capacitor charging and discharging of the ΔΣ ADC is minimal. The buffers therefore help to increase the input impedance of the device. See the Electrical Characteristics table for the typical values of absolute input currents (current flowing into or out of each input) and differential input currents (difference in absolute current between the positive and negative input).

The usable absolute input voltage range of the buffers is (AGND – 0.1 V ≤ VAINP, VAINN ≤ AVDD + 0.1 V). VIN denotes the differential input voltage VIN = VAINP – VAINN between the buffer inputs.

A programmable gain stage follows the buffers. The GAIN bit in the configuration register is used to configure the gain to either 1 or 4.

Equation 4 shows that the differential full-scale input voltage range (FSR) of the device is defined by the gain setting and the reference voltage used:

Equation 4. FSR = ±VREF / Gain

Table 3 shows the corresponding full-scale ranges and least significant bit (LSB) sizes when using the internal 2.048-V reference.

Table 3. Full-Scale Range and LSB Size

GAIN SETTING FSR LSB SIZE
1 ±2.048 V 244.14 nV
4 ±0.512 V 61.04 nV

In order to measure single-ended signals that are referenced to AGND (AINP = VIN, AINN = AGND), connect one of the analog inputs to AGND externally or use the internal AGND connection of the multiplexer (MUX[2:0] settings 011 through 110). The device only uses the code range that represents positive differential voltages when measuring single-ended signals. See the Data Format section for more details.

For signal sources with high output impedance, external buffering may still be necessary. Active buffers can introduce noise as well as offset and gain errors. Consider all of these factors in high-accuracy applications.