JAJSFY4C August   2018  – October 2019 LMR36015-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 System Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power-Good Flag Output
      2. 9.3.2 Enable and Start-up
      3. 9.3.3 Current Limit and Short Circuit
      4. 9.3.4 Undervoltage Lockout and Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Auto Mode
      2. 9.4.2 Forced PWM Operation
      3. 9.4.3 Dropout
      4. 9.4.4 Minimum Switch On-Time
      5. 9.4.5 Spread Spectrum Operation
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design 1: Low Power 24-V, 1.5-A PFM Converter
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1  Custom Design With WEBENCH Tools
          2. 10.2.1.2.2  Choosing the Switching Frequency
          3. 10.2.1.2.3  Setting the Output Voltage
            1. 10.2.1.2.3.1 FB for Adjustable Output
          4. 10.2.1.2.4  Inductor Selection
          5. 10.2.1.2.5  Output Capacitor Selection
          6. 10.2.1.2.6  Input Capacitor Selection
          7. 10.2.1.2.7  CBOOT
          8. 10.2.1.2.8  VCC
          9. 10.2.1.2.9  CFF Selection
            1. 10.2.1.2.9.1 External UVLO
          10. 10.2.1.2.10 Maximum Ambient Temperature
      2. 10.2.2 Application Curves
      3. 10.2.3 Design 2: High Density 12-V, 1.5-A FPWM Converter
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curves
    3. 10.3 What to Do and What Not to Do
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Ground and Thermal Considerations
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 開発サポート
        1. 13.1.1.1 WEBENCH®ツールによるカスタム設計
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 サポート・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

8.5 Electrical Characteristics

Limits apply over operating junction temperature (TJ ) range of –40°C to +150°C, unless otherwise stated. Minimum and Maximum limits(1) are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 24 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
IQ-nonSW Operating quiescent current (non-switching)(2) VEN = 3.3 V (PFM variant only) 18 26 36 µA
ISD Shutdown quiescent current; measured at VIN pin VEN = 0 V 5 µA
ENABLE (EN PIN)
VEN-VCC-H Enable input high level for VCC output VENABLE rising 1.14 V
VEN-VCC-L Enable input low level for VCC output VENABLE falling 0.3 V
VEN-VOUT-H Enable input high level for VOUT VENABLE rising 1.157 1.231 1.3 V
VEN-VOUT-HYS Enable input hysteresis for VOUT Hysteresis below VENABLE-H; falling 110 mV
ILKG-EN Enable input leakage current VEN = 3.3V 0.2 nA
INTERNAL LDO (VCC PIN)
VCC Internal VCC voltage 6 V ≤ VIN ≤ 60 V 4.75 5 5.25 V
VCC-UVLO-Rising Internal VCC undervoltage lockout VCC rising 3.6 3.8 4.0 V
VCC-UVLO-Falling Internal VCC undervoltage lockout VCC falling 3.1 3.3 3.5 V
VOLTAGE REFERENCE (FB PIN)
VOUT-3.3V-Fixed Output voltage 3.23 3.3 3.37 V
VFB Feedback voltage 0.985 1 1.015 V
ILKG-VOUT-3.3V-Fixed Feedback leakage current VOUT = 3.3 V (Fixed Option) 1.4 1.8 µA
ILKG-FB Feedback leakage current FB = 1 V 0.2 nA
CURRENT LIMITS AND HICCUP
ISC High-side current limit(3) 2 2.4 2.8 A
ILS-LIMIT Low-side current limit(3) 1.55 1.8 2.07 A
IL-ZC Zero cross detector threshold PFM variants only 0.02 A
IPEAK-MIN Minimum inductor peak current(3) 0.45 A
IL-NEG Negative current limit(3) FPWM variant only –1.8 –1.4 –0.9 A
POWER GOOD (PGOOD PIN)
VPG-HIGH-UP Power-Good upper threshold - rising % of FB voltage 105% 107% 110%
VPG-LOW-DN Power-Good lower threshold - falling % of FB voltage 90% 93% 95%
VPG-HYS Power-Good hysteresis (rising & falling) % of FB voltage 2%
TPG Power-Good rising/falling edge deglitch delay 80 140 200 µs
VPG-VALID Minimum input voltage for proper Power-Good function 2 V
RPG Power-Good on-resistance VEN = 2.5 V 80 165 Ω
RPG Power-Good on-resistance VEN = 0 V 35 90 Ω
OSCILLATOR
FOSC Internal oscillator frequency 2.1-MHz variant 1.95 2.1 2.35 MHz
FOSC Internal oscillator frequency 400-kHz variant 340 400 460 kHz
MOSFETS
RDS-ON-HS High-side MOSFET ON-resistance IOUT = 0.5 A 225 435 mΩ
RDS-ON-LS Low-side MOSFET ON-resistance IOUT = 0.5 A 150 280 mΩ
(1) MIN and MAX limits are 100% production tested at 25℃. Limits over the operating temperature range verified through correlation using
Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.
(3) The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application.