JAJSFZ6F May   2013  – August 2018 TS3DV642

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Dynamic Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Display Port (DP) Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Docking Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 HDMI Application
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS(1) MIN TYP(2) MAX UNIT
PORT A
RON ON-state resistance D0 to D3 VCC = 3 V, 1.5 V ≤ VI/O ≤ VCC,
II/O = –40 mA		 6.5 9.5 Ω
SCL, SDA, HPD, CEC 6 9.5 Ω
RON(flat)(3) ON-state resistance flatness All I/O VCC = 3 V, VI/O = 1.5 V and VCC,
II/O = –40 mA		 1.5 Ω
ΔRON(4) On-state resistance match between high-speed channels D0 to D3 VCC = 3 V, 1.5 V ≤ VI/O ≤ VCC,
II/O = –40 mA		 0.4 1 Ω
IOFF Leakage under power off All outputs VCC = 0 V, VI/O = 0 to 3.6 V,
VIN = 0 V to 5.5 V		 ±10 µA
PORT B
RON ON-state resistance D0 to D3 VCC = 3 V, 1.5 V ≤ VI/O ≤ VCC,
II/O = –40 mA		 8.2 10.5 Ω
SCL, SDA, HPD, CEC 6 9.5 Ω
RON(flat)(3) ON-state resistance flatness All I/O VCC = 3 V, VI/O = 1.5 V and VCC,
II/O = –40 mA		 1.5 Ω
ΔRON(4) On-state resistance match between high-speed channels D0 to D3 VCC = 3 V, 1.5 V ≤ VI/O ≤ VCC,
II/O = –40 mA		 0.4 1 Ω
IOFF Leakage under power off All outputs VCC = 0 V, VI/O = 0 V to 3.6 V,
VIN = V to 5.5 V		 ±10 µA
DIGITAL INPUTS (SEL1, SEL2, EN)
VIH High-level control input voltage SEL1, SEL2, EN 1.4 V
VIL Low-level control input voltage SEL1, SEL2, EN 0.5 V
IIH Digital input high leakage current SEL1, SEL2, EN VCC = 3.6 V , VIN = VDD ±10 µA
IIL Digital input low leakage current SEL1, SEL2, EN VCC = 3.6 V, VIN = GND ±10 µA
SUPPLY
ICC VCC supply current VCC = 3.6 V, II/O = 0, Normal Operation Mode, EN = H 50 µA
ICC, PD VCC supply current in power-down mode VCC = 3.6 V, II/O = 0, EN = L 6 µA
(1) VI, VO, II, and IO refer to I/O pins, VIN refers to the control inputs.
(2) All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
(3) RON(FLAT) is the difference of RON in a given channel at specified voltages.
(4) ΔRON is the difference of RON from center port to any other ports.