JAJSG05H November 2009 – October 2024 CDC3RL02
PRODUCTION DATA
PIN | Type(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
VBATT | A1 | I | Input to internal LDO |
CLK_OUT1 | A2 | O | Clock output 1 |
VLDO | B1 | O | 1.8V I/O supply for CDC3RL02 and external TCXO |
CLK_REQ1 | B2 | I | Clock request 1 (from peripheral) for Clock output 1 |
MCLK_IN | C1 | I | Master clock input |
CLK_REQ2 | C2 | I | Clock request 2 (from peripheral) for Clock output 2 |
GND | D1 | – | Ground |
CLK_OUT2 | D2 | O | Clock output 2 |
1 | 2 | |
---|---|---|
A | VBATT | CLK_OUT1 |
B | VLDO | CLK_REQ1 |
C | MCLK_LIN | CLK_REQ2 |
D | GND | CLK_OUT2 |