JAJSGB9B January 2010 – October 2018 TLV320DAC3101
PRODUCTION DATA.
The internal clock runs nominally at 8.2 MHz. This is used for various internal timing intervals, de-bounce logic, and interrupts. The MCLK divider must be set in such a way that the divider output is approximately 1 MHz for the timers to be closer to the programmed value.