JAJSGH7B September   2006  – November 2018 TPS2376-H

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション回路
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 ESD Ratings IEC
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Thermal Information
    6. 7.6 Electrical Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Lockout (UVLO)
      2. 8.3.2 Programmable Inrush Current Limit and Fixed Operational Current Limit
      3. 8.3.3 Power Good
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Internal Thresholds
      2. 9.1.2 Detection
      3. 9.1.3 Classification
    2. 9.2 Typical Application
      1. 9.2.1 External Components
        1. 9.2.1.1 Detection Resistor and UVLO Divider
        2. 9.2.1.2 Magnetics
        3. 9.2.1.3 Input Diodes or Diode Bridges
        4. 9.2.1.4 Input Capacitor
        5. 9.2.1.5 Load Capacitor
        6. 9.2.1.6 Transient Suppressor
  10. 10Power Supply Recommendations
    1. 10.1 Maintain Power Signature
    2. 10.2 DC/DC Converter Startup
    3. 10.3 Auxiliary Power Source ORing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Protection
    4. 11.4 ESD
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

7.5 Thermal Information

THERMAL METRIC(1) TPS2376-H UNIT
DDA (SOIC)
8 PINS
RθJA Junction-to-ambient thermal resistance Modified High-K(2) 58.6 °C/W
Modified Low-K(2) 50
Best(2) 45
  1. For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
  2. Tested per JEDEC JESD51, natural convection. The definitions of high-k and low-k are per JESD 51-7 and JESD 51-3. Modified low-k (2 signal - no plane, 3 in. by 3 in. board, 0.062 in. thick, 1 oz. copper) test board with the pad soldered, and an additional 0.12 in.2 of top-side copper added to the pad. Modified high-k is a (2 signal – 2 plane) test board with the pad soldered. The best case thermal resistance is obtained using the recommendations per SLMA002 (2 signal - 2 plane with the pad connected to the plane).