JAJSGI5D November   2018  – June 2022 TLIN1441-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 ESD Ratings, IEC Specification
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Thermal Information
    6. 7.6 Power Supply Characteristics
    7. 7.7 Electrical Characteristics
    8. 7.8 AC Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Test Circuit: Diagrams and Waveforms
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  LIN Pin
        1. 9.3.1.1 LIN Transmitter Characteristics
        2. 9.3.1.2 LIN Receiver Characteristics
          1. 9.3.1.2.1 Termination
      2. 9.3.2  TXD (Transmit Input)
      3. 9.3.3  RXD (Receive Output)
      4. 9.3.4  WAKE (High Voltage Local Wake Up Input)
      5. 9.3.5  WDT/CLK (Pin Programmable Watchdog Delay Input/SPI Clock)
      6. 9.3.6  WDI/SDI (Watchdog Timer Input/SPI Serial Data In)
      7. 9.3.7  PIN/nCS (Pin Watchdog Select/SPI Chip Select)
      8. 9.3.8  LIMP (LIMP Home output – High Voltage Open Drain Output)
      9. 9.3.9  nWDR/SDO (Watchdog Timeout Reset Output/SPI Serial Data Out)
      10. 9.3.10 VSUP (Supply Voltage)
      11. 9.3.11 GND (Ground)
      12. 9.3.12 EN/nINT (Enable Input/Interrupt Output in SPI Mode)
      13. 9.3.13 nRST/nWDR (Reset Output/Watchdog Timeout Reset Output)
      14. 9.3.14 VCC (Supply Output)
      15. 9.3.15 Protection Features
        1. 9.3.15.1 TXD Dominant Time Out (DTO)
        2. 9.3.15.2 Bus Stuck Dominant System Fault: False Wake Up Lockout
        3. 9.3.15.3 Thermal Shutdown
        4. 9.3.15.4 Under Voltage on VSUP
        5. 9.3.15.5 Unpowered Device and LIN Bus
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Mode
      2. 9.4.2 Sleep Mode
      3. 9.4.3 Standby Mode
      4. 9.4.4 Failsafe Mode
      5. 9.4.5 Wake-Up Events
        1. 9.4.5.1 Wake-Up Request (RXD)
        2. 9.4.5.2 Local Wake Up (LWU) via WAKE Terminal
      6. 9.4.6 Mode Transitions
      7. 9.4.7 Voltage Regulator
        1. 9.4.7.1 VCC
        2. 9.4.7.2 Output Capacitance Selection
        3. 9.4.7.3 Low-Voltage Tracking
        4. 9.4.7.4 Power Supply Recommendation
      8. 9.4.8 Watchdog
        1. 9.4.8.1 Watchdog Error Counter
        2. 9.4.8.2 Pin Control Mode
        3. 9.4.8.3 SPI Control Programming
        4. 9.4.8.4 Watchdog Timing
    5. 9.5 Programming
      1. 9.5.1 SPI Communication
        1. 9.5.1.1 Chip Select Not (nCS)
        2. 9.5.1.2 Serial Clock Input (CLK)
        3. 9.5.1.3 Serial Data Input (SDI)
        4. 9.5.1.4 Serial Data Output (SDO)
    6. 9.6 Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Normal Mode Application Note
        2. 10.2.1.2 Standby Mode Application Note
        3. 10.2.1.3 TXD Dominant State Timeout Application Note
      2. 10.2.2 Detailed Design Procedures
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

9.6 Registers

The following tables contain the registers that the device use during SPI communication

Table 9-4 Device ID and Revision
ADDRESSREGISTERVALUEACCESS
‘h00Reserved54R
‘h01Reserved43R
‘h02Reserved41R
‘h03Reserved4ER
‘h04Reserved32R
‘h05DEVICE_ID[7:0] "4"34R
‘h06DEVICE_ID[7:0] "4"34R
‘h07DEVICE_ID[7:0] "1"31R
‘h08DEVICE_ID[7:0] “3” "5"33,35R
‘h09Rev_ID Major01R
‘h0AREV_ID Minor00R
Table 9-5 Device Configuration and Flag Registers
ADDRESSBIT(S)DEFAULTDESCRIPTIONACCESS
'h0B7:62'b00MODE: Modes of Operation

00 = Standby Mode

01 = Sleep Mode

10 = Normal Mode

11 = Reserved

R/W/U
51'b0LIMP_DIS: LIMP Disable

0 = LIMP Enabled

1 = LIMP Disabled

R/W/U
4:32'b00LIMP_SEL_RESET: Selects the method LIMP is reset/turned off

00 = On the third successful input trigger the error counter receives

01 = First correct input trigger

10 = SPI write 1 to h'0B[2]

11 = Reserved

R/W
21'b0LIMP Reset - Writing a one resets LIMP but then clearsR/WC
11'b0FAILSAFE_EN: Fail safe mode enable

0 = Disabled

1 = Enabled

R/W
01'b0DTO_DIS: Dominant timeout Disable

0 = DTO Enabled

1 = DTO Disabled

R/W
'h0C71'b0DTO InterrupR/WC
61'b0UVCC InterruptR/WC
51'b0TSD InterruptR/WC
41'b0SPIERR InterruptR/WC
31'b0WDERR InterruptR/WC
21'b0OVCC InterruptR/WC
11'b0LWU InterruptR/WC
01'b0WUP InterruptR/WC
'h0D7:08'h00ReservedR
'h0E71'b1DTO Interrupt MaskR/W
61'b1UVCC Interrupt MaskR/W
51'b1TSD Interrupt MaskR/W
41'b1SPIERR Interrupt MaskR/W
31'b1WDERR Interrupt MaskR/W
21'b1OVCC Interrupt MaskR/W
11'b1LWU Interrupt MaskR/W
01'b1WUP Interrupt MaskR/W
'h0F7:08'h00ReservedR
'h107:44'b0000ReservedR
3:21'b0nRST_nWDR_SEL: Pin 12 configuration select when in SPI mode.

00 = nRST (Default)

01 = nWDR

10 = Both nRST for UVCC and nWDR for watchdog failure event

11 = Reserved

R/W
11'b0ReservedR
01'b0SOFT_RST: Soft reset of device. Writing a 1 resets the registers to default valuesR/WC
Table 9-6 Device Watchdog Registers
ADDRESSBIT(S)DEFAULTDESCRIPTIONACCESS
'h117:08'h00Read and Write Capable Scratch PadR/W
'h127:08'h00Read and Write Capable Scratch PadR/W
'h1371'b0WD_DIS - Watchdog Function Disable

0 = Enabled

1 = Disabled

R/W
61'b0WD_WINDOW_TIMEOUT_SEL: Configures Watchdog as either a Window or Time-out watchdog

0 = Window

1 = Timeout

R/W
5:42'b00WD_PRE: Watchdog prescalar

00 = Factor 1

01 = Factor 2

10 = Factor 3

11 = Factor 4

R/W
3:22'b00WD_ERR_CNT_SET Sets the watchdog event error counter that upon overflow the watchdog output trigger event taked place. Increases with each error and decreases with each correct WD trigger. Does not go below zero.

00 = Immediate trigger on each WD event

01 = 2-Bit: Triggers on the fifth error event

10 = 3-Bit: Triggers on the ninth error event

11 = Reserved

R/W
1:02'b10WD_ACTION: Selection Action when Watchdog times out or misses a window

00 = nINT is pulled low

01 = VCC is turned off for 100 ms and turned back on

10 = nWDR is toggled high → low → high

11 = Reserved

R/W
'h147:53'b000WD_TIMER - Sets the window or timeout times and is based upon the WD_PRE setting - See Table 9-3R/W
4:14'b0100WD_ERR_CNT: Watchdog error counter: Keeps a running count of the errors up to 15 errorsR
01'b0ReservedR
'h157:08'h00WD_TRIG: Writes to these bits resets the watchdog timer (FF)WC
Note:

For WD_ACTION turning off VCC for 100 ms and turning it back on, causes SPI communication to stop during the off time.