JAJSGJ6B November   2018  – May 2022 UCC27282

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable
      2. 7.3.2 Start-up and UVLO
      3. 7.3.3 Input Stages and Interlock
      4. 7.3.4 Level Shifter
      5. 7.3.5 Output Stage
      6. 7.3.6 Negative Voltage Transients
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select Bootstrap and VDD Capacitor
        2. 8.2.2.2 Estimate Driver Power Losses
        3. 8.2.2.3 Selecting External Gate Resistor
        4. 8.2.2.4 Delays and Pulse Width
        5. 8.2.2.5 External Bootstrap Diode
        6. 8.2.2.6 VDD and Input Filter
        7. 8.2.2.7 Transient Protection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

GUID-A654F79C-2EEB-4F94-8123-671E154D5AC3-low.gifFigure 5-1 DRC Package10-Pin VSON With Exposed Thermal PadTop View
GUID-85ABFB49-5905-42A7-ACE4-9251981F5698-low.gifFigure 5-3 DRM Package8-Pin SONTop View
GUID-13BCC348-389A-4AEE-8208-5B60216DAD5D-low.gifFigure 5-2 D Package8-Pin SOICTop View
GUID-2466DB76-9952-4092-B9DA-6128183AA64E-low.gifFigure 5-4 DPR Package10-Pin SONTop View
Table 5-1 Pin Functions
PIN I/O(1) DESCRIPTION
Name D DRC DRM DPR
EN n/a 6 n/a n/a I Enable input. When this pin is pulled high, it will enable the driver. If left floating or pulled low, it will disable the driver. 1 nF filter capacitor is recommended for high-noise systems.
HB 2 3 2 2 P High-side bootstrap supply. The bootstrap diode is on-chip but the external bootstrap capacitor is required. Connect positive side of the bootstrap capacitor to this pin. Typical recommended value of HB bypass capacitor is 0.1 μF, This value primarily depends on the gate charge of the high-side MOSFET. When using external boot diode, connect cathode of the diode to this pin.
HI 5 7 5 7 I High-side input.
HO 3 4 3 3 O High-side output. Connect to the gate of the high-side power MOSFET or one end of external gate resistor, when used.
HS 4 5 4 4 P High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this pin.
LI 6 8 6 8 I Low-side input
LO 8 10 8 10 O Low-side output. Connect to the gate of the low-side power MOSFET or one end of external gate resistor, when used.
NC n/a 2 n/a 5,6 — Not connected internally.
VDD 1 1 1 1 P Positive supply to the low-side gate driver. Decouple this pin to VSS. Typical decoupling capacitor value is 1 μF. When using an external boot diode, connect the anode to this pin.
VSS 7 9 7 9 G Negative supply terminal for the device which is generally the system ground.
Thermal pad n/a - - - — Connect to a large thermal mass trace (generally IC ground plane) to improve thermal performance. This can only be electrically connected to VSS.
(1) P = Power, G = Ground, I = Input, O = Output, I/O = Input/Output