JAJSGL8E December   2014  – October 2024 TCA9617B

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7.   Parameter Measurement Information
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Bidirectional Level Translation
      2. 6.3.2 Low to High Transition Characteristics
      3. 6.3.3 High-to-Low Transition Characteristics
    4. 6.4 Device Functional Modes
  9. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Standard Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Pullup Resistor Sizing
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Star Application
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curves
      3. 7.2.3 Series Application
        1. 7.2.3.1 Design Requirements
        2. 7.2.3.2 Detailed Design Procedure
        3. 7.2.3.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  10. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 商標
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  11. 9 Revision History
  12. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information

7.1 Application Information

A typical application is shown in Figure 7-1. In this example, the system controller is running on a 0.9V I2C bus, and the target is connected to a 2.5V bus. Both buses are running at 400kHz. Decoupling capacitors are required, but are not shown in Figure 7-6 for simplicity.

The TCA9617B is 5V tolerant so no additional circuits are required to translate between 0.8V to 5.5V bus voltages and 2.7V to 5.5V bus voltages.

When the A side of the TCA9617B is pulled low by a driver on the I2C bus, a comparator detects the falling edge when the signal level goes below 30% of VCCA and cause the internal driver on the B side to turn on. The B-side is first pulled down to 0V, and then settles to 0.5V. When the B side of the TCA9617B falls below 0.4V, the TCA9617B detects the falling edge, turn on the internal driver on the A side and pull the A-side pin down to ground.

On the B-side bus of the TCA9617B, the clock and data lines has a positive offset from ground equal to the VOL of the TCA9617B. After the eighth clock pulse, the data line is pulled to the VOL of the target device, which is close to ground in this example. At the end of the acknowledge, the level rises only to the low level set by the driver of the TCA9617B for a short delay (approximately 0.5V), while the A-side bus rises above 30% of VCCA and then continues high.

Although the TCA9617B has a single application, the device can exist in multiple configurations. Figure 7-1 shows the standard configuration for the TCA9617B. Multiple TCA9617Bs can be connected either in star configuration (Figure 7-4) or in series configuration (Figure 7-5). The design requirements, detailed design procedure, and application curves in Section 7.2.1 are valid for all three configurations.