JAJSGU3H March   2012  – March 2019 SN65HVD72 , SN65HVD75 , SN65HVD78

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Power Dissipation
    7. 7.7  Switching Characteristics: 250 kbps Device (SN65HVD72) Bit Time ≥ 4 µs
    8. 7.8  Switching Characteristics: 20 Mbps Device (SN65HVD75) Bit Time ≥50 ns
    9. 7.9  Switching Characteristics: 50 Mbps Device (SN65HVD78) Bit Time ≥20 ns
    10. 7.10 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Data Rate and Bus Length
        2. 10.2.1.2 Stub Length
        3. 10.2.1.3 Bus Loading
        4. 10.2.1.4 Receiver Failsafe
        5. 10.2.1.5 Transient Protection
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 External Transient Protection
        2. 10.2.2.2 Isolated Bus Node Design
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 関連リンク
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

7.5 Electrical Characteristics

over recommended operating range (unless otherwise specified)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|VOD| Driver differential output voltage magnitude RL = 60 Ω, 375 Ω on each output to
–7 V to 12 V		 See Figure 10 1.5 2 V
RL = 54 Ω (RS-485) See Figure 11 1.5 2
RL = 100 Ω (RS-422), TJ ≥ 0°C
VCC ≥ 3.2 V 		2 2.5
Δ|VOD| Change in magnitude of driver differential output voltage RL = 54 Ω, CL = 50 pF –50 0 50 mV
VOC(SS) Steady-state common-mode output voltage Center of two 27-Ω load resistors 1 VCC/2 3 V
ΔVOC Change in differential driver output common-mode voltage Center of two 27-Ω load resistors –50 0 50 mV
VOC(PP) Peak-to-peak driver common-mode output voltage Center of two 27-Ω load resistors 200 mV
COD Differential output capacitance 15 pF
VIT+ Positive-going receiver differential input voltage threshold See (1) –70 –20 mV
VIT– Negative-going receiver differential input voltage threshold –200 –150 See (1) mV
VHYS Receiver differential input voltage threshold hysteresis (VIT+ – VIT–) 50 80 mV
VOH Receiver high-level output voltage IOH = –8 mA 2.4 VCC – 0.3 V
VOL Receiver low-level output voltage IOL = 8 mA 0.2 0.4 V
II Driver input, driver enable, and receiver enable input current –2 2 µA
IOZ Receiver output high-impedance current VO = 0 V or VCC, RE at VCC –1 1 µA
IOS Driver short-circuit output current –160 160 mA
II Bus input current (disabled driver) VCC = 3 to 3.6 V or
VCC = 0 V
DE at 0 V		 SN65HVD72 SN65HVD75 VI = 12 V 75 150 µA
VI = –7 V –100 –40
SN65HVD78 VI = 12 V 240 333
VI = –7 V –267 –180
ICC Supply current (quiescent) Driver and receiver enabled DE = VCC, RE = GND
No load 		750 950 µA
Driver enabled, receiver disabled DE = VCC, RE = VCC
No load 		300 500
Driver disabled, receiver enabled DE = GND, RE = GND
No load		 600 800
Driver and receiver disabled DE = GND, D = open
RE = VCC, No load 		0.1 2
Supply current (dynamic) See Typical Characteristics
TTSD Thermal shutdown junction temperature 170 °C
(1) Under any specific conditions, VIT+ is assured to be at least VHYS higher than VIT–.