JAJSGU3H March   2012  – March 2019 SN65HVD72 , SN65HVD75 , SN65HVD78

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Power Dissipation
    7. 7.7  Switching Characteristics: 250 kbps Device (SN65HVD72) Bit Time ≥ 4 µs
    8. 7.8  Switching Characteristics: 20 Mbps Device (SN65HVD75) Bit Time ≥50 ns
    9. 7.9  Switching Characteristics: 50 Mbps Device (SN65HVD78) Bit Time ≥20 ns
    10. 7.10 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Data Rate and Bus Length
        2. 10.2.1.2 Stub Length
        3. 10.2.1.3 Bus Loading
        4. 10.2.1.4 Receiver Failsafe
        5. 10.2.1.5 Transient Protection
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 External Transient Protection
        2. 10.2.2.2 Isolated Bus Node Design
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 関連リンク
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

8 Parameter Measurement Information

Input generator rate is 100 kbps, 50% duty cycle, rise or fall time is less than 6 ns, output impedance is 50 Ω.

SN65HVD72 SN65HVD75 SN65HVD78 s0301_01_llsE11.gifFigure 10. Measurement of Driver Differential Output Voltage With Common-Mode Load
SN65HVD72 SN65HVD75 SN65HVD78 s0302_01_llsE11.gifFigure 11. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
SN65HVD72 SN65HVD75 SN65HVD78 pmi_dr_sw_llsE11.gifFigure 12. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
SN65HVD72 SN65HVD75 SN65HVD78 s0304_01_llsE11.gif
D at 3 V to test non-inverting output, D at 0 V to test inverting output.
Figure 13. Measurement of Driver Enable and Disable Times With Active High Output and Pulldown Load
SN65HVD72 SN65HVD75 SN65HVD78 s0305_01_llsE11.gif
D at 0 V to test non-inverting output, D at 3 V to test inverting output.
Figure 14. Measurement of Driver Enable and Disable Times With Active Low Output and Pullup Load
SN65HVD72 SN65HVD75 SN65HVD78 s0306_01_llsE11.gifFigure 15. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
SN65HVD72 SN65HVD75 SN65HVD78 s0307_01_llsE11.gifFigure 16. Measurement of Receiver Enable and Disable Times With Driver Enabled
SN65HVD72 SN65HVD75 SN65HVD78 s0308_01_llsE11.gifFigure 17. Measurement of Receiver Enable Times With Driver Disabled