JAJSH18A March   2019  – September 2019 TPS7A78

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ハーフブリッジ構成の標準的な回路図
      2.      フルブリッジ構成の標準的な回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Active Bridge Control
      2. 8.3.2 Full-Bridge (FB) and Half-Bridge (HB) Configurations
      3. 8.3.3 4:1 Switched-Capacitor Voltage Reduction
      4. 8.3.4 Undervoltage Lockout Circuits (VUVLO_SCIN) and (VUVLO_LDO_IN)
      5. 8.3.5 Dropout Voltage Regulation
      6. 8.3.6 Current Limit
      7. 8.3.7 Programmable Power-Fail Detection
      8. 8.3.8 Power-Good (PG) Detection
      9. 8.3.9 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 Dropout Mode
      3. 8.4.3 Disabled Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Recommended Capacitor Types
      2. 9.1.2 Input and Output Capacitors Requirements
      3. 9.1.3 Startup Behavior
      4. 9.1.4 Load Transient
      5. 9.1.5 Standby Power and Output Efficiency
      6. 9.1.6 Reverse Current
      7. 9.1.7 Switched-Capacitor Stage Output Impedance
      8. 9.1.8 Power Dissipation (PD)
      9. 9.1.9 Estimating Junction Temperature
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Calculating the Cap-Drop Capacitor CS
          1. 9.2.2.1.1 CS Calculations for the Typical Design
        2. 9.2.2.2 Calculating the Surge Resistor RS
          1. 9.2.2.2.1 RS Calculations for the Typical Design
        3. 9.2.2.3 Checking for the Device Maximum ISHUNT Current
          1. 9.2.2.3.1 ISHUNT Calculations for the Typical Design
        4. 9.2.2.4 Calculating the Bulk Capacitor CSCIN
          1. 9.2.2.4.1 CSCIN Calculations for the Typical Design
        5. 9.2.2.5 Calculating the PFD Pin Resistor Dividers for a Power-Fail Detection
          1. 9.2.2.5.1 PFD Pin Resistor Divider Calculations for the Typical Design
        6. 9.2.2.6 Summary of the Typical Application Design Components
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. 12.1.1.1 評価基板
        2. 12.1.1.2 SIMPLIS モデル
      2. 12.1.2 デバイスの項目表記
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

7.7 Typical Characteristics

at operating temperature TJ = 25°C, VAC supply = 120 VRMS per 60 Hz, full-bridge (FB) bridge configuration, CS = 1.0 µF, CSCIN = 220 µF, CSC1 = 1.0 µF, CSC2 = 2.2 µF, CLDO_IN = 10 µF, CLDO_OUT = 1.0 µF, and IOUT = 1 mA (unless otherwise noted)
TPS7A78 D023_SBVS343_TPS7A78.gif
VAC = 70 VRMS to 270 VRMS, VLDO_OUT = 5.0 V
Figure 1. VLDO_OUT Accuracy vs VAC Supply
TPS7A78 D001_SBVS343_TPS7A78.gif
VSCIN = 17 V, VLDO_OUT ≤ 3.4 V
Figure 3. VLDO_OUT Accuracy vs DC Supply on the SCIN Pin
TPS7A78 D0016_SBVS343_TPS7A78.gif
VSCIN = 17 V, VLDO_OUT = 3.3 V
Figure 5. VLDO_OUT vs IOUT DC Supply on the SCIN Pin
TPS7A78 D0015_SBVS343_TPS7A78.gif
Figure 7. VIT(PFD,FALLING) Threshold vs Temperature
TPS7A78 D025_SBVS343_TPS7A78.gif
FB configuration, scope bandwidth = 10 MHz,
IOUT = 1 mA
Figure 9. VLDO_OUT Ripple for FB Configuration
TPS7A78 D012_SBVS343_TPS7A78.gif
CS = 2.2 µF, CSCIN = 22 µF, CLDO_IN = 1.0 µF, IOUT = 10 mA
Figure 11. Fast Startup With Larger Than the Required Cap-Drop Capacitor for 10-mA IOUT
TPS7A78 D003_SBVS343_TPS7A78.gif
VSCIN = 19 V, VLDO_OUT ≤ 3.4 V
Figure 13. IOUT Current Limit
TPS7A78 D024_SBVS343_TPS7A78.gif
VLDO_OUT = 5.0 V, IOUT = 0 mA to 120 mA
Figure 2. VLDO_OUT Accuracy vs IOUT
TPS7A78 D002_SBVS343_TPS7A78.gif
VSCIN = 19 V, VLDO_OUT ≤ 3.4 V
Figure 4. VLDO_OUT Accuracy vs IOUT DC Supply on the SCIN Pin
TPS7A78 D0017_SBVS343_TPS7A78.gif
VSCIN = 19 V, VLDO_OUT = 3.3 V
Figure 6. VLDO_OUT vs IOUT DC Supply on the SCIN Pin
TPS7A78 D011_SBVS343_TPS7A78.gif
Figure 8. VIT(PG,FALLING) and VIT(PG,RISING) Thresholds vs Temperature
TPS7A78 D026_SBVS343_TPS7A78.gif
FB configuration, scope bandwidth = 10 MHz,
IOUT = 120 mA
Figure 10. VLDO_OUT Ripple for FB Configuration
TPS7A78 D019_SBVS343_TPS7A78.gif
CS = 100 nF, CSCIN = 22 µF, CLDO_IN = 1.0 µF, IOUT = 10 mA
Figure 12. Slow Startup With the Minimum Required Cap-Drop Capacitor for 10-mA IOUT