JAJSH81B April   2019  – February 2021 TPS929120-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Bias and Power
        1. 7.3.1.1 Power Supply (SUPPLY)
        2. 7.3.1.2 5-V Low-Drop-Out Linear Regulator (VLDO)
        3. 7.3.1.3 Undervoltage Lockout (UVLO) and Power-On-Reset (POR)
        4. 7.3.1.4 Programmable Low Supply Warning
      2. 7.3.2 Constant Current Output
        1. 7.3.2.1 Reference Current With External Resistor (REF)
        2. 7.3.2.2 64-Step Programmable High-Side Constant-Current Output
      3. 7.3.3 PWM Dimming
        1. 7.3.3.1 PWM Dimming Frequency
        2. 7.3.3.2 PWM Generator
        3. 7.3.3.3 Linear Brightness Control
        4. 7.3.3.4 Exponential Brightness Control
        5. 7.3.3.5 External Clock Input for PWM Generator (CLK)
        6. 7.3.3.6 External PWM Input ( PWM0 and PWM1)
      4. 7.3.4 On-chip 8-bit Analog-to-Digital Converter (ADC)
      5. 7.3.5 Diagnostic and Protection in Normal State
        1. 7.3.5.1  Fault Masking
        2. 7.3.5.2  Supply Undervoltage Lockout Diagnostics in Normal State
        3. 7.3.5.3  Low-Supply Warning Diagnostics in Normal State
        4. 7.3.5.4  Reference Diagnostics in Normal State
        5. 7.3.5.5  Pre-Thermal Warning and Overtemperature Protection in Normal State
        6. 7.3.5.6  Communication Loss Diagnostic in Normal State
        7. 7.3.5.7  LED Open-Circuit Diagnostics in Normal State
        8. 7.3.5.8  LED Short-circuit Diagnostics in Normal State
        9. 7.3.5.9  On-Demand Off-State Invisible Diagnostics
        10. 7.3.5.10 On-Demand Off-State Single-LED Short-Circuit (SS) Diagnostics
        11. 7.3.5.11 Automatic Single-LED Short-Circuit (AutoSS) Detection in Normal State
        12. 7.3.5.12 EEPROM CRC Error in Normal State
        13.       47
      6. 7.3.6 Diagnostic and Protection in Fail-Safe States
        1. 7.3.6.1 Fault Masking
        2. 7.3.6.2 Supply UVLO Diagnostics in Fail-Safe States
        3. 7.3.6.3 Low-supply Warning Diagnostics in Fail-Safe states
        4. 7.3.6.4 Reference Diagnostics at Fail-Safe States
        5. 7.3.6.5 Overtemperature Protection in Fail-Safe State
        6. 7.3.6.6 LED Open-circuit Diagnostics in Fail-Safe State
        7. 7.3.6.7 LED Short-circuit Diagnostics in Fail-safe State
        8. 7.3.6.8 EEPROM CRC Error in Fail-safe State
        9.       57
    4. 7.4 Device Functional Modes
      1. 7.4.1 POR State
      2. 7.4.2 Initialization State
      3. 7.4.3 Normal State
      4. 7.4.4 Fail-Safe States
      5. 7.4.5 Program State
      6. 7.4.6 Programmable Output Failure State
      7. 7.4.7 ERR Output
      8. 7.4.8 Register Default Data
    5. 7.5 Programming
      1. 7.5.1 FlexWire Protocol
        1. 7.5.1.1 Protocol Overview
        2. 7.5.1.2 UART Interface Address Setting
        3. 7.5.1.3 Status Response
        4. 7.5.1.4 Synchronization Byte
        5. 7.5.1.5 Device Address Byte
        6. 7.5.1.6 Register Address Byte
        7. 7.5.1.7 Data Frame
        8.       76
        9. 7.5.1.8 CRC Frame
        10. 7.5.1.9 Burst Mode
      2. 7.5.2 Registers Lock
      3. 7.5.3 All Registers CRC Check
      4. 7.5.4 EEPROM Programming
        1. 7.5.4.1 Chip Selection by Pulling REF Pin High
        2. 7.5.4.2 Chip Selection by ADDR Pins configuration
        3. 7.5.4.3 EEPROM Register Access and Burn
        4. 7.5.4.4 EEPROM Program State Exit
        5. 7.5.4.5 Reading Back EEPROM
    6. 7.6 Register Maps
      1. 7.6.1 FullMap Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Smart Rear Lamp With Distributed LED drivers
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  12. 12Mechanical, Packaging, and Orderable Information

7.3.3.2 PWM Generator

The 12-bit PWM generator constructs the cyclical PWM output based on a 12-bit digital binary input to control the output current ON and OFF. Basically the PWM generator counts 256 pulses at base high frequency for PWM output cycle period and counts number of pulses determined by MSB 8 bits of 12-bit binary input at the same frequency for PWM ON period. The LSB 4 bits of 12-bit binary input is used to set up the dithering to realize total 12-bit resolution. The base high frequency is generated by internal oscillator, which is 256 times of the frequency programmable by CONF_PWMFREQ. Figure 7-2 is the signal path diagram for PWM generator.

GUID-9C59B997-97CD-47EB-B527-5B81E9E2EE62-low.gifFigure 7-2 PWM Generator Path Diagram