JAJSH81B April   2019  – February 2021 TPS929120-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Bias and Power
        1. 7.3.1.1 Power Supply (SUPPLY)
        2. 7.3.1.2 5-V Low-Drop-Out Linear Regulator (VLDO)
        3. 7.3.1.3 Undervoltage Lockout (UVLO) and Power-On-Reset (POR)
        4. 7.3.1.4 Programmable Low Supply Warning
      2. 7.3.2 Constant Current Output
        1. 7.3.2.1 Reference Current With External Resistor (REF)
        2. 7.3.2.2 64-Step Programmable High-Side Constant-Current Output
      3. 7.3.3 PWM Dimming
        1. 7.3.3.1 PWM Dimming Frequency
        2. 7.3.3.2 PWM Generator
        3. 7.3.3.3 Linear Brightness Control
        4. 7.3.3.4 Exponential Brightness Control
        5. 7.3.3.5 External Clock Input for PWM Generator (CLK)
        6. 7.3.3.6 External PWM Input ( PWM0 and PWM1)
      4. 7.3.4 On-chip 8-bit Analog-to-Digital Converter (ADC)
      5. 7.3.5 Diagnostic and Protection in Normal State
        1. 7.3.5.1  Fault Masking
        2. 7.3.5.2  Supply Undervoltage Lockout Diagnostics in Normal State
        3. 7.3.5.3  Low-Supply Warning Diagnostics in Normal State
        4. 7.3.5.4  Reference Diagnostics in Normal State
        5. 7.3.5.5  Pre-Thermal Warning and Overtemperature Protection in Normal State
        6. 7.3.5.6  Communication Loss Diagnostic in Normal State
        7. 7.3.5.7  LED Open-Circuit Diagnostics in Normal State
        8. 7.3.5.8  LED Short-circuit Diagnostics in Normal State
        9. 7.3.5.9  On-Demand Off-State Invisible Diagnostics
        10. 7.3.5.10 On-Demand Off-State Single-LED Short-Circuit (SS) Diagnostics
        11. 7.3.5.11 Automatic Single-LED Short-Circuit (AutoSS) Detection in Normal State
        12. 7.3.5.12 EEPROM CRC Error in Normal State
        13.       47
      6. 7.3.6 Diagnostic and Protection in Fail-Safe States
        1. 7.3.6.1 Fault Masking
        2. 7.3.6.2 Supply UVLO Diagnostics in Fail-Safe States
        3. 7.3.6.3 Low-supply Warning Diagnostics in Fail-Safe states
        4. 7.3.6.4 Reference Diagnostics at Fail-Safe States
        5. 7.3.6.5 Overtemperature Protection in Fail-Safe State
        6. 7.3.6.6 LED Open-circuit Diagnostics in Fail-Safe State
        7. 7.3.6.7 LED Short-circuit Diagnostics in Fail-safe State
        8. 7.3.6.8 EEPROM CRC Error in Fail-safe State
        9.       57
    4. 7.4 Device Functional Modes
      1. 7.4.1 POR State
      2. 7.4.2 Initialization State
      3. 7.4.3 Normal State
      4. 7.4.4 Fail-Safe States
      5. 7.4.5 Program State
      6. 7.4.6 Programmable Output Failure State
      7. 7.4.7 ERR Output
      8. 7.4.8 Register Default Data
    5. 7.5 Programming
      1. 7.5.1 FlexWire Protocol
        1. 7.5.1.1 Protocol Overview
        2. 7.5.1.2 UART Interface Address Setting
        3. 7.5.1.3 Status Response
        4. 7.5.1.4 Synchronization Byte
        5. 7.5.1.5 Device Address Byte
        6. 7.5.1.6 Register Address Byte
        7. 7.5.1.7 Data Frame
        8.       76
        9. 7.5.1.8 CRC Frame
        10. 7.5.1.9 Burst Mode
      2. 7.5.2 Registers Lock
      3. 7.5.3 All Registers CRC Check
      4. 7.5.4 EEPROM Programming
        1. 7.5.4.1 Chip Selection by Pulling REF Pin High
        2. 7.5.4.2 Chip Selection by ADDR Pins configuration
        3. 7.5.4.3 EEPROM Register Access and Burn
        4. 7.5.4.4 EEPROM Program State Exit
        5. 7.5.4.5 Reading Back EEPROM
    6. 7.6 Register Maps
      1. 7.6.1 FullMap Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Smart Rear Lamp With Distributed LED drivers
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  12. 12Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

TJ = –40°C to 150°C, V(SUPPLY) = 5-40 V, For digital outputs, C(LOAD) = 20 pF, (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BIAS
V(SUPPLY) Operating input voltage 4.5 12 40 V
IQ(ON) Quiescent current, all-channels-on V(SUPPLY) = 12 V, R(REF) =31.6 kΩ, all-output ON 10 mA
IQ(OFF) Quiescent current, all-channels-off V(SUPPLY) = 12 V, R(REF) = 31.6 kΩ, all-output OFF 3.5 mA
I(FAULT) Quiescent current, fail-safe state fault mode V(SUPPLY) = 12 V, fail-safe state, all-output OFF, ERR = LOW 2.5 2.85 mA
V(POR_rising) Power-on-reset rising threshold 4 4.2 4.4 V
V(POR_falling) Power-on-reset falling threshold 3.8 4 4.2 V
V(LDO) LDO output voltage V(SUPPLY) > 5.6 V, I(LDO) = 40 mA, CONF_LDO = 0b 4.75 5 5.25 V
V(SUPPLY) > 5.6 V, I(LDO) = 40 mA, CONF_LDO = 1b 4.18 4.4 4.62 V
I(LDO) LDO output current capability 80 mA
I(LDO_LIMIT) LDO output current limit 100 mA
V(LDO_DROP) LDO maximum dropout voltage I(LDO) = 80 mA 0.5 0.9 V
V(LDO_DROP) LDO maximum dropout voltage I(LDO) = 50 mA 0.3 0.6 V
V(LDO_POR_rising) LDO power-on-reset rising threshold 2.75 3 3.25 V
V(LDO_POR_falling) LDO power-on-reset falling threshold 2.5 2.75 3 V
C(LDO) Supported LDO loading capacitance range 1 10 µF
f(OSC) Internal oscillator frequency -2.5% 32.15 +2.5% MHz
ERR
VIL(ERR) Input logic low voltage, ERR 0.7 V
VIH(ERR) Input logic high voltage, ERR 2 V
I(pd_ERR) ERR pull-down current capability V(ERR) = 0.4 V 3 6 9 mA
Ilkg(ERR) ERR leakage current 1 µA
FLEXWIRE INTERFACE
VIL(RX) Input logic low voltage, RX 0.7 V
VIH(RX) Input logic high voltage, RX 2 V
VOL(TX) Low-level output voltage TX, Isink = 5 mA, 0 0.3 V
VOH(TX) High-level output voltage TX, Isource = 5 mA, Vpull-up = 5 V 4.7 5 V
Ilkg TX, RX –1 1 µA
ADDRESS, FS
VIL(IO) Input logic low voltage, ADDR2/CLK, ADDR1/PWM1, ADDR0/PWM0, FS 0.7 V
VIH(IO) Input logic high voltage, ADDR2/CLK, ADDR1/PWM1, ADDR0/PWM0, FS 2 V
R(PD_ADDR) Internal pull down resistance, ADDR2/CLK, ADDR1/PWM1, ADDR0/PWM0 100 kΩ
R(PD_FS) Internal pull down resistance, FS 100 kΩ
ADC
DNL Differential nonlinearity –1(1) 1(1) LSB
INL Integral nonlinearity –2(1) 2(1) LSB
OUTPUT DRIVERS
f(PWM_200) 200-Hz selection 200 Hz
f(PWM_1000) 1-kHz selection 1000 Hz
ΔI(OUT_d2d) Device-to-device accuracy ΔI(OUT_d2d) = 1- Iavg(OUT) / Iideal(OUT) R(REF) = 8.45 kOhm, CONF_REFRANGE = 11b, DC=63 –5 0 5 %
R(REF) = 8.45 kOhm, CONF_REFRANGE = 10b, DC=63 –5 0 5
R(REF) = 8.45 kOhm, CONF_REFRANGE = 01b, DC=63 –5 0 5
R(REF) = 8.45 kOhm, CONF_REFRANGE = 00b, DC=63 –5 0 5
ΔI(OUT_c2c) Channel-to-channel accuracy ΔI(OUT_c2c) = 1- I(OUTx) / Iavg(OUT) R(REF) = 8.45 kOhm, CONF_REFRANGE = 11b, DC=63 –3 0 3 %
R(REF) = 8.45 kOhm, CONF_REFRANGE = 10b, DC=31 –3 0 3
R(REF) = 8.45 kOhm, CONF_REFRANGE = 01b, DC=15 –5 0 5
R(REF) = 31.6 kOhm, CONF_REFRANGE = 01b, DC=12 –7 0 7
I(OUT_75mA) R(REF) = 8.45 kOhm, CONF_REFRANGE = 11b, DC=63 75 mA
I(OUT_50mA) R(REF) = 12.7 kOhm, CONF_REFRANGE = 11b, DC=63 50 mA
I(OUT_20mA) R(REF) = 31.6 kOhm, CONF_REFRANGE = 11b, DC=63 20 mA
I(OUT_1mA) R(REF) = 31.6 kOhm, CONF_REFRANGE = 01b, DC = 12 1 mA
V(OUT_drop) output dropout voltage R(REF) = 8.45 kOhm, CONF_REFRANGE = 11b, DC=38, I(OUTx) = 45 mA 400 700 mV
V(OUT_drop) output dropout voltage R(REF) = 8.45 kOhm, CONF_REFRANGE = 11b, DC=63, I(OUTx) = 75 mA 600 1000 mV
R(REF) 1 50 kΩ
C(REF) 0 4.7 nF
V(REF) 1.235 V
K(REF_11) CONF_REFRANGE = 11b 512
K(REF_10) CONF_REFRANGE = 10b 256
K(REF_01) CONF_REFRANGE = 01b 128
K(REF_00) CONF_REFRANGE = 00b 64
I(REF_OPEN_th) 10 µA
V(REF_SHORT_th) 0.6 V
DIAGNOSTICS
V(OPEN_th_rising) LED open rising threshold V(SUPPLY) - V(OUTx) 200 400 600 mV
V(OPEN_th_falling) LED open falling threshold V(SUPPLY) - V(OUTx) 300 500 700 mV
V(OPEN_th_hyst) 100 mV
V(SG_th_rising) Short-to-ground
rising threshold		 0.8 0.9 1 V
V(SG_th_falling) Short-to-ground
falling threshold		 1.1 1.2 1.3 V
V(SG_th_hyst) Short-to-ground
hysteresis		 0.3 V
EEPROM
N(EEP) Number of programming cycles. V(SUPPLY) = 12 V 1000
MISC
T(PRETSD) Pre-thermal warning threshold 135 oC
T(PRETSD_HYS) Pre-thermal warning hysteresis 5 oC
T(TSD) Over-temperature
protection threshold		 160 175 190 oC
T(TSD_HYS) Over-temperature
protection hysteresis		 15 oC
(1) Guaranteed by design only