JAJSHF0B February   2019  – November 2019 BQ25887

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Power-On-Reset
      2. 8.3.2  Device Power Up from Input Source
        1. 8.3.2.1 Poor Source Qualification
        2. 8.3.2.2 Input Source Type Detection
          1. 8.3.2.2.1 PSEL Sets Input Current Limit
          2. 8.3.2.2.2 Force Input Current Limit Detection
        3. 8.3.2.3 Power Up REGN Regulator (LDO)
        4. 8.3.2.4 Converter Power Up
      3. 8.3.3  Input Current Optimizer (ICO)
      4. 8.3.4  Battery Charging Management
        1. 8.3.4.1 Autonomous Charging Cycle
        2. 8.3.4.2 Battery Charging Profile
        3. 8.3.4.3 Cell Balancing During Charging
        4. 8.3.4.4 Charging Termination
        5. 8.3.4.5 Thermistor Qualification
          1. 8.3.4.5.1 JEITA Guideline Compliance in Charge Mode
        6. 8.3.4.6 Charging Safety Timer
      5. 8.3.5  Integrated 16-Bit ADC for Monitoring
      6. 8.3.6  Status Outputs
        1. 8.3.6.1 Power Good Indicator (PG)
        2. 8.3.6.2 Charging Status Indicator (STAT)
        3. 8.3.6.3 Interrupt to Host
      7. 8.3.7  Input Current Limit on ILIM Pin
      8. 8.3.8  Voltage and Current Monitoring
        1. 8.3.8.1 Voltage and Current Monitoring in Boost Mode
          1. 8.3.8.1.1 Input Over-Voltage Protection
          2. 8.3.8.1.2 Input Under-Voltage Protection
      9. 8.3.9  Thermal Regulation and Thermal Shutdown
        1. 8.3.9.1 Thermal Protection in Boost Mode
      10. 8.3.10 Battery Protection
      11. 8.3.11 Serial Interface
        1. 8.3.11.1 Data Validity
        2. 8.3.11.2 START and STOP Conditions
        3. 8.3.11.3 Byte Format
        4. 8.3.11.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.3.11.5 Slave Address and Data Direction Bit
        6. 8.3.11.6 Single Write and Read
        7. 8.3.11.7 Multi-Write and Multi-Read
    4. 8.4 Device Functional Modes
      1. 8.4.1 Host Mode and Default Mode
    5. 8.5 Register Maps
      1. 8.5.1  Cell Voltage Regulation Limit Register (Address = 00h) [reset = A0h]
        1. Table 8. REG00 Register Field Descriptions
      2. 8.5.2  Charger Current Limit Register (Address = 01h) [reset = 5Eh]
        1. Table 9. REG01 Register Field Descriptions
      3. 8.5.3  Input Voltage Limit Register (Address = 02h) [reset = 84h]
        1. Table 10. REG02 Register Field Descriptions
      4. 8.5.4  Input Current Limit Register (Address = 03h) [reset = 39h ]
        1. Table 11. REG03 Register Field Descriptions
      5. 8.5.5  Precharge and Termination Current Limit Register (Address = 04h) [reset = 22h]
        1. Table 12. REG04 Register Field Descriptions
      6. 8.5.6  Charger Control 1 Register (Address = 05h) [reset = 9Dh]
        1. Table 13. REG05 Register Field Descriptions
      7. 8.5.7  Charger Control 2 Register (Address = 06h) [reset = 7Dh]
        1. Table 14. REG06 Register Field Descriptions
      8. 8.5.8  Charger Control 3 Register (Address = 07h) [reset = 00h]
        1. Table 15. REG07 Register Field Descriptions
      9. 8.5.9  Charger Control 4 Register (Address = 08h) [reset = 0Dh]
        1. Table 16. REG08 Register Field Descriptions
      10. 8.5.10 Reserved Register (Address = 09h) [reset = 00h]
        1. Table 17. REG09 Register Field Descriptions
      11. 8.5.11 ICO Current Limit in Use Register (Address = 0Ah) [reset = XXh]
        1. Table 18. REG0A Register Field Descriptions
      12. 8.5.12 Charger Status 1 Register (Address = 0Bh) [reset = XXh]
        1. Table 19. REG0B Register Field Descriptions
      13. 8.5.13 Charger Status 2 Register (Address = 0Ch) [reset = XXh]
        1. Table 20. REG0C Register Field Descriptions
      14. 8.5.14 NTC Status Register (Address = 0Dh) [reset = 0Xh]
        1. Table 21. REG0D Register Field Descriptions
      15. 8.5.15 FAULT Status Register (Address = 0Eh) [reset = XXh]
        1. Table 22. REG0E Register Field Descriptions
      16. 8.5.16 Charger Flag 1 Register (Address = 0Fh) [reset = 00h]
        1. Table 23. REG0F Register Field Descriptions
      17. 8.5.17 Charger Flag 2 Register (Address = 10h) [reset = 00h]
        1. Table 24. REG10 Register Field Descriptions
      18. 8.5.18 FAULT Flag Register (Address = 11h) [reset = 00h]
        1. Table 25. REG11 Register Field Descriptions
      19. 8.5.19 Charger Mask 1 Register (Address = 12h) [reset = 00h]
        1. Table 26. REG12 Register Field Descriptions
      20. 8.5.20 Charger Mask 2 Register (Address = 13h) [reset = 00h]
        1. Table 27. REG13 Register Field Descriptions
      21. 8.5.21 FAULT Mask Register (Address = 14h) [reset = 00h]
        1. Table 28. REG14 Register Field Descriptions
      22. 8.5.22 ADC Control Register (Address = 15h) [reset = 30h]
        1. Table 29. REG15 Register Field Descriptions
      23. 8.5.23 ADC Function Disable Register (Address = 16h) [reset = 00h]
        1. Table 30. REG16 Register Field Descriptions
      24. 8.5.24 IBUS ADC 1 Register (Address = 17h) [reset = 00h]
        1. Table 31. REG17 Register Field Descriptions
      25. 8.5.25 IBUS ADC 0 Register (Address = 18h) [reset = 00h]
        1. Table 32. REG18 Register Field Descriptions
      26. 8.5.26 ICHG ADC 1 Register (Address = 19h) [reset = 00h]
        1. Table 33. REG19 Register Field Descriptions
      27. 8.5.27 ICHG ADC 0 Register (Address = 1Ah) [reset = 00h]
        1. Table 34. REG1A Register Field Descriptions
      28. 8.5.28 VBUS ADC 1 Register (Address = 1Bh) [reset = 00h]
        1. Table 35. REG1B Register Field Descriptions
      29. 8.5.29 VBUS ADC 0 Register (Address = 1Ch) [reset = 00h]
        1. Table 36. REG1C Register Field Descriptions
      30. 8.5.30 VBAT ADC 1 Register (Address = 1Dh) [reset = 00h]
        1. Table 37. REG1D Register Field Descriptions
      31. 8.5.31 VBAT ADC 0 Register (Address = 1Eh) [reset = 00h]
        1. Table 38. REG1E Register Field Descriptions
      32. 8.5.32 VCELLTOP ADC 1 Register (Address = 1Fh) [reset = 00h]
        1. Table 39. REG1F Register Field Descriptions
      33. 8.5.33 VCELLTOP ADC 0 Register (Address = 20h) [reset = 00h]
        1. Table 40. REG20 Register Field Descriptions
      34. 8.5.34 TS ADC 1 Register (Address = 21h) [reset = 00h]
        1. Table 41. REG21 Register Field Descriptions
      35. 8.5.35 TS ADC 0 Register (Address = 22h) [reset = 00h]
        1. Table 42. REG22 Register Field Descriptions
      36. 8.5.36 TDIE ADC 1 Register (Address = 23h) [reset = 00h]
        1. Table 43. REG23 Register Field Descriptions
      37. 8.5.37 TDIE ADC 0 Register (Address = 24h) [reset = 00h]
        1. Table 44. REG24 Register Field Descriptions
      38. 8.5.38 Part Information Register (Address = 25h) [reset = 28h]
        1. Table 45. REG25 Register Field Descriptions
      39. 8.5.39 VCELLBOT ADC 1 Register (Address = 26h) [reset = 00h]
        1. Table 46. REG26 Register Field Descriptions
      40. 8.5.40 VCELLBOT ADC 0 Register (Address = 27h) [reset = 00h]
        1. Table 47. REG27 Register Field Descriptions
      41. 8.5.41 Cell Balancing Control 1 Register (Address = 28h) [reset = 2Ah]
        1. Table 48. REG28 Register Field Descriptions
      42. 8.5.42 Cell Balancing Control 2 Register (Address = 29h) [reset = F4h]
        1. Table 49. REG29 Register Field Descriptions
      43. 8.5.43 Cell Balancing Status and Control Register (Address = 2Ah) [reset = 81h]
        1. Table 50. REG2A Register Field Descriptions
      44. 8.5.44 Cell Balancing Flag Register (Address = 2Bh) [reset = 00h]
        1. Table 51. REG2B Register Field Descriptions
      45. 8.5.45 Cell Balancing Mask Register (Address = 2Ch) [reset = 00h]
        1. Table 52. REG2C Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input (VBUS / PMID) Capacitor
        3. 9.2.2.3 Output (VSNS) Capacitor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

7.5 Electrical Characteristics

VVBUS_UVLO_RISING< VVBUS < VVBUS_OV, TJ = -40°C to+125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
QUIESCENT CURRENTS
IBAT Battery discharge current (BAT) VBAT = 9 V, No VBUS, SCL, SDA = 0 V or 1.8 V, TJ=25C, ADC Disabled 12 14 µA
VBAT = 9 V, No VBUS, SCL, SDA = 0 V or 1.8 V, TJ < 85C, ADC Disabled 12 20 µA
IVBUS_HIZ Input supply current (VBUS) in HIZ VBUS = 5 V, High-Z Mode, no battery, ADC Disabled, 25℃ 30 38 µA
VBUS = 5 V, High-Z Mode, no battery, ADC Disabled, <85℃ 30 48 µA
IVBUS Input supply current (VBUS) VBUS = 5 V, VBAT = 7.6 V, converter not switching 1.5 3 mA
VBUS = 5 V, VBAT = 7.6 V, converter switching 3 mA
VBUS/VBAT POWER UP
VVBUS_OP VBUS operating range 3.9 6.2 V
VVBUS_UVLO_RISING VBUS rising for active I2C, no battery VBUS rising 3.3 3.68 V
VVBUS_OV VBUS over-voltage rising threshold VBUS rising 6.2 6.6 V
VBUS over-voltage falling threshold VBUS falling 5.9 6.4 V
VBAT_UVLO_RISING Battery for active I2C VBAT rising 3.7 4 4.42 V
VPOORSRC_FALLING Bad adapter detection threshold VBUS falling below VPOORSRC_FALLING 3.7 V
IPOORSRC Bad adapter detection current source 15 mA
BATTERY CHARGER
VCELLREG_RANGE Typical charge voltage regulation range 3.4 4.6 V
VCELLREG_STEP Typical charge voltage step 5 mV
VCELLREG_ACC Charge voltage VREG = 4.20 V, TJ = 0°C to 85°C, 4.179 4.2 4.221 V
VCELLREG_ACC Charge voltage VREG = 4.35 V, TJ = 0°C to 85°C 4.328 4.35 4.372 V
ICHG_RANGE Charge current regulation range 100 2200 mA
ICHG_STEP Charge current regulation step 50 mA
ICHG_ACC Fast Charge current regulation accuracy ICHG = 1000 mA, VBAT = 6.2 V or 7.6 V, TJ = 0°C to 85°C -7.5 7.5 %
ICHG_ACC Fast Charge current regulation accuracy ICHG = 500mA, VBAT = 6.2 V or 7.6 V, TJ = 0°C to 85°C -15 15 %
ICHG_ACC Fast Charge current regulation accuracy ICHG = 250 mA, VBAT = 6.2 V or 7.6 V, TJ = 0°C to 85°C -25 25 %
IPRECHG_RANGE Precharge current range 50 800 mA
IPRECHG_STEP Typical precharge current step 50 mA
IPRECHG_ACC Precharge current accuracy VBAT = 5.2 V, IPRECHG = 200 mA, TJ = 25°C 170 237 mA
VBAT = 5.2 V, IPRECHG = 200 mA, TJ = 0°C to 85°C 150 245 mA
ITERM_RANGE Termination current range 50 800 mA
ITERM_STEP Typical termination current step 50 mA
ITERM_ACC Termination current accuracy ICHG = 1.5A, ITERM = 150 mA, TJ = 25°C 143 157 mA
ICHG = 1.5A, ITERM = 150 mA, TJ = 0°C to 85°C 120 180 mA
ICHG = 1.5A, ITERM = 50 mA, TJ = 25°C 45 60 mA
ICHG = 1.5A, ITERM = 50 mA, TJ = 0°C to 85°C 22 75 mA
VCELL_SHORT_RISING Short Battery Voltage rising threshold
to start pre-charging 		VCELL rising 2.05 2.2 2.35 V
VCELL_SHORT_FALLING Short Battery Voltage falling
threshold to stop pre-charging		 VCELL falling 1.85 2 2.15 V
IBAT_SHORT Low Battery Voltage trickle charging current VTOPCELL<2.2V, VBOTCELL<VREG-VRCHG; Or VBOTCELL<2.2V, VTOPCELL<VREG-VRCHG 100 mA
VCELL_LOWV_RISING VCELL LOWV Rising threshold to start fast-charging VCELL rising, VBATLOW = 2.8 V 2.65 2.8 2.95 V
VCELL rising, VBATLOWV = 3.0 V 2.85 3 3.15 V
VCELL_LOWV_FALLING VCELL LOWV falling threshold to start fast-charging VCELL falling, VBATLOW = 2.8 V 2.45 2.6 2.75 V
VCELL falling, VBATLOWV = 3.0 V 2.65 2.8 2.95 V
VCELL_RECHG Recharge threshold below VCELLREG  VCELL falling, VCELL_RECHG[1:0] = 01 100 mV
RON_QHS (Q2) High-side switching MOSFET on-resistance between SW and SNS (Q2) TJ =  25°C 32 35 mΩ
TJ = – 40°C to 125°C 32 47 mΩ
RON_QLS (Q3) Low-side switching MOSFET on-resistance between SW and GND (Q3) TJ = 25°C 42 46 mΩ
TJ = – 40°C to 125°C 42 63 mΩ
IBAT_DISCHG BAT Discharge current source VBAT = 8V, EN_BAT_DISCHG = 1 8 11.5 16 mA
INPUT VOLTAGE / CURRENT REGULATION
VINDPM_RANGE Input voltage regulation range 3.9 5.5 V
VINDPM_STEP Input voltage regulation step 100 mV
VINDPM Input voltage limit VINDPM = 3.9 V 3.783 3.9 4.017 V
VINDPM = 4.4 V 4.268 4.4 4.532 V
IINDPM_RANGE Input current regulation range 500 3300 mA
IINDPM_STEP Input current regulation step 100 mA
IINDPM_ACC Input current regulation limit IINDPM = 500 mA 438 469 500 mA
IINDPM = 900 mA 765 832 900 mA
IINDPM = 2500 mA 2125 2312 2500 mA
IINDPM = 3000 mA 2550 2775 3000 mA
KILIM IINMAX = KILIM/RILIM Input Current regulation by ILIM pin  1110 A x Ω
IINDPM Input current regulation limit, IINMAX = KILIM/RILIM Input Current regulation by ILIM pin = 0.5A 457 505 553 mA
Input Current regulation by ILIM pin = 0.9A 839 909 980 mA
Input Current regulation by ILIM pin = 1.5A 1413 1518 1624 mA
RON_QBLK (Q1) Blocking MOSFET on-resistance between VBUS and PMID (QBLK) TJ = 25°C 33 37 mΩ
TJ = – 40°C to 125°C 33 51 mΩ
THERMAL REGULATION AND THERMAL SHUTDOWN
TREG Junction temperature regulation accuracy TREG = 120°C 120 °C
TSHUT_RISING Thermal Shutdown Rising threshold Temperature Increasing 150 °C
Thermal Shutdown Falling threshold Temperature Decreasing 120 °C
JEITA THERMISTOR COMPARATOR (BOOST MODE)
VT1 TS pin voltage rising. T1 (0°C) threshold, Charge suspended below this temperature. As Percentage to REGN 72.75 73.25 73.75 %
VT1_HYS TS pin voltage falling. Charge re-enabled to ICHG/2 and VREG above this temperature As Percentage to REGN 1.3 %
VT2 TS pin voltage rising. T2 (10°C) threshold, charge set to ICHG/2 and VREG below this temperature As Percentage to REGN 67.75 68.25 68.75 %
VT2_HYS TS pin voltage falling. Charge set to ICHG and VREG above this temperature As Percentage to REGN 1.2 %
VT3 TS pin voltage falling. T3 (45°C) threshold, charge set to ICHG and 8.1 V above this temperature. As Percentage to REGN 44.25 44.75 45.25 %
VT3_HYS TS pin voltage rising. Charge set to ICHG and VREG below this temperature As Percentage to REGN 1 %
VT5 TS pin voltage falling. T5 (60°C) threshold, charge suspended above this temperature. As Percentage to REGN 33.875 34.375 34.875 %
VT5_HYS TS pin voltage rising. Charge set to ICHG and 8.1 V below this temperature As Percentage to REGN 1.35 %
BOOST MODE CONVERTER
FSW PWM switching frequency Oscillator frequency 1.35 1.5 1.65 MHz
CELL BALANCING
ICB_MAX Maximum recommended cell balancing current VCELL = 4.2V, RCBSET = 9.5Ω, RDSON_QCBX = 1Ω 400 mA
RDSON_QCBH MOSFET on resistance between BAT and MID Cell balance enabled (REG0x2A[0] = 1); VCELL_HS > 3.7 V, VCELL_HS > VCELL_LS, VBAT - VMID - VMID > 80 mV, ICB ≤ 400 mA 1 1.2 Ω
RDSON_QCBL MOSFET on resistance between MID and GND Cell balance enabled (REG0x2A[0] = 1); VCELL_LS > 3.7 V, VCELL_LS > VCELL_HS, VMID - (VBAT - VMID) > 80 mV, ICB ≤ 400 mA 1 1.2 Ω
VCBEN_RISING Cell balance function qualification threshold Cell balance enabled rising threshold 3.65 3.7 3.75 V
VCBEN_HYS Cell balance function qualification hysteresis Cell balance enabled falling hysteresis 200 mV
VQUAL_TH_RANGE Cell balance pre-qualification mode to qualification mode threshold range Cell balance enabled (REG0X2A[0]=1); VCELL_LS or VCELL_HS>3.7V, increase the voltage delta between the two cells 40 180 mV
VQUAL_TH_STEP Cell balance pre-qualification mode to qualification mode threshold step size Cell balance enabled (REG0X2A[0]=1); VCELL_LS or VCELL_HS>3.7V, increase the voltage delta between the two cells 10 mV
VQUAL_TH Cell balance pre-qualification mode to qualification mode threshold. Cell balance enabled (REG0X2A[0]=1); VCELL_LS or VCELL_HS>3.7V, increase the voltage delta between the two cells 80 mV
VDIFF_START_RANGE Balance discharge start cell voltage difference threshold range Cell balance enabled (REG0x2A[0] = 1); Difference between the two cells to turn on cell balancing MOSFET  40 190 mV
VDIFF_START_STEP Balance discharge start cell voltage difference threshold step size Cell balance enabled (REG0x2A[0] = 1); Difference between the two cells to turn on cell balancing MOSFET  10 mV
VDIFF_START Balance discharge start cell voltage difference threshold Cell balance enabled (REG0x2A[0] = 1); Difference between the two cells to turn on cell balancing MOSFET set to 120mV (REG0x29[3:0] = 1000) 120 mV
VDIFF_START Balance discharge start cell voltage difference threshold Cell balance enabled (REG0x2A[0] = 1); Difference between the two cells to turn on cell balancing MOSFET set to 80mV (REG0x29[3:0] = 0100) 80 mV
VDIFF_END_RANGE Balance discharge stop cell voltage difference threshold range Cell balance enabled (REG0x2A[0] = 1); Difference between the two cells to turn off cell balancing MOSFET  30 100 mV
VDIFF_END_STEP Balance discharge stop cell voltage difference threshold step size Cell balance enabled (REG0x2A[0] = 1); Difference between the two cells to turn off cell balancing MOSFET  10 mV
VDIFF_END Balance discharge stop cell voltage difference threshold Cell balance enabled (REG0x2A[0] = 1); Difference between the two cells to turn off cell balancing MOSFET set to (REG0x29[3:0] = 1000, REG0x28[7:5]=010) 70 mV
VDIFF_END Balance discharge stop cell voltage difference threshold Cell balance enabled (REG0x28[7] = 1); Difference between the two cells to turn off cell balancing MOSFET set to 45mV (REG0x29[3:0] = 0100, REG0x28[7:5]=001) 40 mV
VCELL_OVP_RISING Cell over voltage rising threshold VCELL rising, as percentage of VCELLREG 102.5 104 105 %
VCELL_OVP_FALLING Cell over voltage falling threshold VCELL rising, as percentage of VCELLREG 100.8 102 103.3 %
IQCBX_OC Cell Balance MOSFET over-current protection ICB > 500mA 400 500 600 mA
IMID_BIAS MID pin bias current Voltage difference between the two battery cells ≤ 400mV 15 µA
REGN LDO
VREGN REGN LDO output voltage VVBUS = 5 V, IREGN = 20 mA 4.7 4.8 5.15 V
IREGN REGN LDO current limit VVBUS = 5 V, VREGN = 3.8 V 50 mA
Analog-to-Digital Converter (ADC)
tADC_CONV Conversion time, each measurement ADC_SAMPLE[1:0] = 11 24 ms
ADC_SAMPLE[1:0] = 10 12 ms
ADC_SAMPLE[1:0] = 01 6 ms
ADC_SAMPLE[1:0] = 00 3 ms
ADCRES Effective resolution ADC_SAMPLE[1:0] = 11 14 15 bits
ADC_SAMPLE[1:0] = 10 13 14 bits
ADC_SAMPLE[1:0] = 01 12 13 bits
ADC_SAMPLE[1:0] = 00 10 12 bits
ADC MEASUREMENT RANGES AND LSB
IBUS_ADC_RANGE ADC BUS current range 0 4 A
IBUS_ADC_LSB ADC BUS current LSB 1 mA
IBAT_ADC_RANGE ADC BAT current range 0 4 A
IBAT_ADC_LSB ADC BAT current LSB 1 mA
VBUS_ADC_RANGE ADC BUS voltage range 0 6.5 V
VBUS_ADC_LSB ADC BUS voltage LSB 1 mV
VBAT_ADC_RANGE ADC BAT voltage range 0 10 V
VBAT_ADC_LSB ADC BAT voltage LSB 1 mV
VCELLTOP_ADC_RANGE ADC MID voltage range 0 5 V
VCELLTOP_ADC_LSB ADC MID voltage LSB 1 mV
VCELLBOT_ADC_RANGE ADC MID voltage range 0 5 V
VCELLBOT_ADC_LSB ADC MID voltage LSB 1 mV
VTS_ADC_RANGE ADC TS voltage range 20 80 %
VTS_ADC_LSB ADC TS voltage LSB 0.098 %
VTDIE_ADC_RANGE ADC Die temperature range 0 150 °C
VTDIE_ADC_LSB ADC Die temperature LSB 0.5 °C
I2C INTERFACE (SCL, SDA)
VIH Input high threshold level, SDA and SCL Pull-up rail 1.8 V 1.3 V
VIL Input low threshold level Pull-up rail 1.8 V 0.4 V
VOL Output low threshold level Sink current = 5 mA 0.4 V
IBIAS High level leakage current Pull-up rail 1.8 V 1 uA
LOGIC I/O PIN (CD, PSEL)
VIH_CD Input high threshold level, CD 1.3 V
VIL_CD Input low threshold level, CD 0.4 V
IIN_BIAS_CD High level leakage current, CD Pull-up rail 1.8 V 2.5 uA
VIH_PSEL Input high threshold level, PSEL 1.3 V
VIL_PSEL Input low threshold level, PSEL 0.4 V
IIN_BIAS_PSEL High level leakage current, PSEL Pull-up rail 1.8 V 1 uA
LOGIC O PIN (/INT, /PG, STAT)
VOL Output low threshold level Sink current = 5 mA 0.4 V
IOUT_BIAS High level leakage current Pull-up rail 1.8 V 1 µA