JAJSHF0B February   2019  – November 2019 BQ25887

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Power-On-Reset
      2. 8.3.2  Device Power Up from Input Source
        1. 8.3.2.1 Poor Source Qualification
        2. 8.3.2.2 Input Source Type Detection
          1. 8.3.2.2.1 PSEL Sets Input Current Limit
          2. 8.3.2.2.2 Force Input Current Limit Detection
        3. 8.3.2.3 Power Up REGN Regulator (LDO)
        4. 8.3.2.4 Converter Power Up
      3. 8.3.3  Input Current Optimizer (ICO)
      4. 8.3.4  Battery Charging Management
        1. 8.3.4.1 Autonomous Charging Cycle
        2. 8.3.4.2 Battery Charging Profile
        3. 8.3.4.3 Cell Balancing During Charging
        4. 8.3.4.4 Charging Termination
        5. 8.3.4.5 Thermistor Qualification
          1. 8.3.4.5.1 JEITA Guideline Compliance in Charge Mode
        6. 8.3.4.6 Charging Safety Timer
      5. 8.3.5  Integrated 16-Bit ADC for Monitoring
      6. 8.3.6  Status Outputs
        1. 8.3.6.1 Power Good Indicator (PG)
        2. 8.3.6.2 Charging Status Indicator (STAT)
        3. 8.3.6.3 Interrupt to Host
      7. 8.3.7  Input Current Limit on ILIM Pin
      8. 8.3.8  Voltage and Current Monitoring
        1. 8.3.8.1 Voltage and Current Monitoring in Boost Mode
          1. 8.3.8.1.1 Input Over-Voltage Protection
          2. 8.3.8.1.2 Input Under-Voltage Protection
      9. 8.3.9  Thermal Regulation and Thermal Shutdown
        1. 8.3.9.1 Thermal Protection in Boost Mode
      10. 8.3.10 Battery Protection
      11. 8.3.11 Serial Interface
        1. 8.3.11.1 Data Validity
        2. 8.3.11.2 START and STOP Conditions
        3. 8.3.11.3 Byte Format
        4. 8.3.11.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.3.11.5 Slave Address and Data Direction Bit
        6. 8.3.11.6 Single Write and Read
        7. 8.3.11.7 Multi-Write and Multi-Read
    4. 8.4 Device Functional Modes
      1. 8.4.1 Host Mode and Default Mode
    5. 8.5 Register Maps
      1. 8.5.1  Cell Voltage Regulation Limit Register (Address = 00h) [reset = A0h]
        1. Table 8. REG00 Register Field Descriptions
      2. 8.5.2  Charger Current Limit Register (Address = 01h) [reset = 5Eh]
        1. Table 9. REG01 Register Field Descriptions
      3. 8.5.3  Input Voltage Limit Register (Address = 02h) [reset = 84h]
        1. Table 10. REG02 Register Field Descriptions
      4. 8.5.4  Input Current Limit Register (Address = 03h) [reset = 39h ]
        1. Table 11. REG03 Register Field Descriptions
      5. 8.5.5  Precharge and Termination Current Limit Register (Address = 04h) [reset = 22h]
        1. Table 12. REG04 Register Field Descriptions
      6. 8.5.6  Charger Control 1 Register (Address = 05h) [reset = 9Dh]
        1. Table 13. REG05 Register Field Descriptions
      7. 8.5.7  Charger Control 2 Register (Address = 06h) [reset = 7Dh]
        1. Table 14. REG06 Register Field Descriptions
      8. 8.5.8  Charger Control 3 Register (Address = 07h) [reset = 00h]
        1. Table 15. REG07 Register Field Descriptions
      9. 8.5.9  Charger Control 4 Register (Address = 08h) [reset = 0Dh]
        1. Table 16. REG08 Register Field Descriptions
      10. 8.5.10 Reserved Register (Address = 09h) [reset = 00h]
        1. Table 17. REG09 Register Field Descriptions
      11. 8.5.11 ICO Current Limit in Use Register (Address = 0Ah) [reset = XXh]
        1. Table 18. REG0A Register Field Descriptions
      12. 8.5.12 Charger Status 1 Register (Address = 0Bh) [reset = XXh]
        1. Table 19. REG0B Register Field Descriptions
      13. 8.5.13 Charger Status 2 Register (Address = 0Ch) [reset = XXh]
        1. Table 20. REG0C Register Field Descriptions
      14. 8.5.14 NTC Status Register (Address = 0Dh) [reset = 0Xh]
        1. Table 21. REG0D Register Field Descriptions
      15. 8.5.15 FAULT Status Register (Address = 0Eh) [reset = XXh]
        1. Table 22. REG0E Register Field Descriptions
      16. 8.5.16 Charger Flag 1 Register (Address = 0Fh) [reset = 00h]
        1. Table 23. REG0F Register Field Descriptions
      17. 8.5.17 Charger Flag 2 Register (Address = 10h) [reset = 00h]
        1. Table 24. REG10 Register Field Descriptions
      18. 8.5.18 FAULT Flag Register (Address = 11h) [reset = 00h]
        1. Table 25. REG11 Register Field Descriptions
      19. 8.5.19 Charger Mask 1 Register (Address = 12h) [reset = 00h]
        1. Table 26. REG12 Register Field Descriptions
      20. 8.5.20 Charger Mask 2 Register (Address = 13h) [reset = 00h]
        1. Table 27. REG13 Register Field Descriptions
      21. 8.5.21 FAULT Mask Register (Address = 14h) [reset = 00h]
        1. Table 28. REG14 Register Field Descriptions
      22. 8.5.22 ADC Control Register (Address = 15h) [reset = 30h]
        1. Table 29. REG15 Register Field Descriptions
      23. 8.5.23 ADC Function Disable Register (Address = 16h) [reset = 00h]
        1. Table 30. REG16 Register Field Descriptions
      24. 8.5.24 IBUS ADC 1 Register (Address = 17h) [reset = 00h]
        1. Table 31. REG17 Register Field Descriptions
      25. 8.5.25 IBUS ADC 0 Register (Address = 18h) [reset = 00h]
        1. Table 32. REG18 Register Field Descriptions
      26. 8.5.26 ICHG ADC 1 Register (Address = 19h) [reset = 00h]
        1. Table 33. REG19 Register Field Descriptions
      27. 8.5.27 ICHG ADC 0 Register (Address = 1Ah) [reset = 00h]
        1. Table 34. REG1A Register Field Descriptions
      28. 8.5.28 VBUS ADC 1 Register (Address = 1Bh) [reset = 00h]
        1. Table 35. REG1B Register Field Descriptions
      29. 8.5.29 VBUS ADC 0 Register (Address = 1Ch) [reset = 00h]
        1. Table 36. REG1C Register Field Descriptions
      30. 8.5.30 VBAT ADC 1 Register (Address = 1Dh) [reset = 00h]
        1. Table 37. REG1D Register Field Descriptions
      31. 8.5.31 VBAT ADC 0 Register (Address = 1Eh) [reset = 00h]
        1. Table 38. REG1E Register Field Descriptions
      32. 8.5.32 VCELLTOP ADC 1 Register (Address = 1Fh) [reset = 00h]
        1. Table 39. REG1F Register Field Descriptions
      33. 8.5.33 VCELLTOP ADC 0 Register (Address = 20h) [reset = 00h]
        1. Table 40. REG20 Register Field Descriptions
      34. 8.5.34 TS ADC 1 Register (Address = 21h) [reset = 00h]
        1. Table 41. REG21 Register Field Descriptions
      35. 8.5.35 TS ADC 0 Register (Address = 22h) [reset = 00h]
        1. Table 42. REG22 Register Field Descriptions
      36. 8.5.36 TDIE ADC 1 Register (Address = 23h) [reset = 00h]
        1. Table 43. REG23 Register Field Descriptions
      37. 8.5.37 TDIE ADC 0 Register (Address = 24h) [reset = 00h]
        1. Table 44. REG24 Register Field Descriptions
      38. 8.5.38 Part Information Register (Address = 25h) [reset = 28h]
        1. Table 45. REG25 Register Field Descriptions
      39. 8.5.39 VCELLBOT ADC 1 Register (Address = 26h) [reset = 00h]
        1. Table 46. REG26 Register Field Descriptions
      40. 8.5.40 VCELLBOT ADC 0 Register (Address = 27h) [reset = 00h]
        1. Table 47. REG27 Register Field Descriptions
      41. 8.5.41 Cell Balancing Control 1 Register (Address = 28h) [reset = 2Ah]
        1. Table 48. REG28 Register Field Descriptions
      42. 8.5.42 Cell Balancing Control 2 Register (Address = 29h) [reset = F4h]
        1. Table 49. REG29 Register Field Descriptions
      43. 8.5.43 Cell Balancing Status and Control Register (Address = 2Ah) [reset = 81h]
        1. Table 50. REG2A Register Field Descriptions
      44. 8.5.44 Cell Balancing Flag Register (Address = 2Bh) [reset = 00h]
        1. Table 51. REG2B Register Field Descriptions
      45. 8.5.45 Cell Balancing Mask Register (Address = 2Ch) [reset = 00h]
        1. Table 52. REG2C Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input (VBUS / PMID) Capacitor
        3. 9.2.2.3 Output (VSNS) Capacitor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

8.3.5 Integrated 16-Bit ADC for Monitoring

The device includes a 16-bit ADC to monitor critical system information based on the device’s modes of operation. The control of the ADC is done through the ADC Control Register (Address = 15h) [reset = 30h]. The ADC_EN bit provides the ability to enable and disable the ADC to conserve power. The ADC_RATE bit allows continuous conversion or one-shot behavior. After a one-shot conversion finishes, the ADC_EN bit is cleared, and must be re-asserted to start a new conversion.

To enable the ADC, the ADC_EN bit must be set to ‘1’. The ADC is allowed to operate if either the VVBUS>VVBUS_UVLO_RISING or VBAT>VBAT_UVLO_RISING is valid. If no adapter is present, and the VBAT is less than VBAT_UVLO_RISING, the device will not perform an ADC measurement, nor update the ADC read-back values in REG17 through REG24. Additionally, the device will immediately reset ADC_EN bit without sending any interrupt. The same will happen if the ADC is enabled when all ADC channels are disabled. It is recommended to read back ADC_EN after setting it to '1' to ensure ADC is running a conversion. If the charger changes mode (for example, if adapter is connected, EN_HIZ goes to '1', or CD goes high,) while an ADC conversion is running, the conversion is interrupted. Once the mode change is complete, the ADC resumes conversion, starting with the channel where it was interrupted. When device is in HIZ mode, ADC conversion can still be enabled through I2C. In HIZ mode, device power up internally to start ADC convertion and turn back down when ADC conversion is completed.

When TS_ADC conversion performs in battery only mode, the REGN is powered and extra battery current would be drawn. Battery current can be kept low by disabling the TS_ADC conversion in battery only mode.

The integrated ADC has two rate conversion options: a one-shot mode and a continuous conversion mode set by the ADC_RATE bit. By default, all ADC parameters will be converted in one-shot or continuous conversion mode unless disabled in the ADC Function Disable Register (Address = 16h) [reset = 00h]. If an ADC parameter is disabled by setting the corresponding bit in REG16, then the read-back value in the corresponding register will be from the last valid ADC conversion or the default POR value (all zeros if no conversions have taken place). If an ADC parameter is disabled in the middle of an ADC measurement cycle, the device will finish the conversion of that parameter, but will not convert the parameter starting the next conversion cycle. Even though no conversion takes place when all ADC measurement parameters are disabled, the ADC circuitry is active and ready to begin conversion as soon as one of the bits in the ADC Function Disable register is set to ‘0’. If all channels are disabled in one-shot conversion mode, the ADC_EN bit is cleared.

The ADC_DONE_STAT and ADC_DONE_FLAG bits signal when a conversion is completed in one-shot mode only. This event produces an INT pulse, which can be masked with ADC_DONE_MASK. During continuous conversion mode, the ADC_DONE_STAT bit has no meaning and will be '0'. The ADC_DONE_FLAG bit will remain unchanged in continuous conversion mode.

ADC conversion operates independently of the faults present in the device. ADC conversion will continue even after a fault has occurred (such as one that causes the power stage to be disabled), and the host must set ADC_EN = ‘0’ to disable the ADC. ADC conversion is interrupted upon adapter plug-in, and will only resume until after Input Source Type Detection is complete. ADC readings are only valid for DC states and not for transients. When host writes ADC_EN = 0, the ADC stops immediately, and ADC measurement values correspond to last valid ADC reading.

A recommended method to exit ADC conversion is described below:

  1. Write ADC_RATE to one-shot, and the ADC will stop at the end of a complete cycle of conversions, or
  2. Disable all ADC conversion channels, and the ADC will stop at the end of the current measurement.