JAJSHO2C July   2019  – May 2024 ISO7021

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1.     Pin Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics 5V Supply
    10. 6.10 Supply Current Characteristics 5V Supply
    11. 6.11 Electrical Characteristics 3.3V Supply
    12. 6.12 Supply Current Characteristics 3.3V Supply
    13. 6.13 Electrical Characteristics 2.5V Supply
    14. 6.14 Supply Current Characteristics 2.5V Supply
    15. 6.15 Electrical Characteristics 1.8V Supply
    16. 6.16 Supply Current Characteristics 1.8V Supply
    17. 6.17 Switching Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Refresh
      2. 8.3.2 Electromagnetic Compatibility (EMC) Considerations
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device I/O Schematics
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Insulation Lifetime
      2. 9.1.2 Intrinsic Safety
        1. 9.1.2.1 Schedule of Limitations
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

6.6 Insulation Specifications

PARAMETER TEST CONDITIONS SPECIFICATIONS UNIT
8-D
IEC 60664-1
CLR External clearance(1) Side 1 to side 2 distance through air 4 mm
CPG External creepage(1) Side 1 to side 2 distance across package surface 4 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) >17 µm
CTI Comparative tracking index IEC 60112; UL 746A >600 V
Material Group According to IEC 60664-1 I
Overvoltage category Rated mains voltage ≤ 150VRMS I-IV
Rated mains voltage ≤ 300VRMS I-III
DIN EN IEC 60747-17 (VDE 0884-17)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 566 VPK
VIOWM Maximum isolation working voltage AC voltage (sine wave); time-dependent dielectric breakdown (TDDB) test; 400 VRMS
DC voltage 566 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM , t = 60s (qualification); VTEST = 1.2 × VIOTM, t = 1s (100% production) 4242 VPK
VIMP Maximum impulse voltage(2) Tested in air, 1.2/50μs waveform per IEC 62368-1 5000 VPK
VIOSM Maximum surge isolation voltage(3) VIOSM ≥ 1.3 x VIMP; Tested in oil (qualification test), 1.2/50μs waveform per IEC 62368-1 10000 VPK
qpd Apparent charge(4) Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60s; Vpd(m) = 1.2 × VIORM , tm = 10s ≤ 5 pC
Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60s;
Vpd(m) = 1.6 × VIORM , tm = 10s		 ≤ 5
Method b: At routine test (100% production); 
Vini = 1.2 x VIOTM, tini = 1s; 
Vpd(m) = 1.875 x VIORM, tm = 1s (method b1) or 
Vpd(m) = Vini, tm = tini (method b2)		 ≤ 5
CIO Barrier capacitance, input to output(5) VIO = 0.4 × sin (2πft), f = 1MHz 1 pF
RIO Insulation resistance, input to output(5) VIO = 500V,  TA = 25°C > 1012 Ω
VIO = 500V,  100°C ≤ TA ≤ 150°C > 1011
VIO = 500V at  TS = 150°C > 109
Pollution degree 2
Climatic category 55/125/
21
UL 1577
VISO Withstand isolation voltage VTEST = VISO , t = 60s (qualification); VTEST = 1.2 × VISO , t = 1s (100% production) 3000 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) Testing is carried out in air to determine the surge immunity of the package.
(3) Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.