JAJSHR0E March   2017  – July 2022 LMH1297

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Recommended SMBus Interface Timing Specifications
    7. 7.7 Serial Parallel Interface (SPI) Timing Specifications
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  4-Level Input Pins and Thresholds
      2. 8.3.2  Equalizer (EQ) and Cable Driver (CD) Mode Control
        1. 8.3.2.1 EQ/CD_SEL Control
        2. 8.3.2.2 OUT0_SEL and SDI_OUT_SEL Control
      3. 8.3.3  Input Carrier Detect
      4. 8.3.4  –6-dB Splitter Mode Launch Amplitude for SDI_IO+ (EQ Mode Only)
      5. 8.3.5  Continuous Time Linear Equalizer (CTLE)
        1. 8.3.5.1 Line-Side Adaptive Cable Equalizer (SDI_IO+ in EQ mode)
        2. 8.3.5.2 Host-Side Adaptive PCB Trace Equalizer (IN0± in CD Mode)
      6. 8.3.6  Clock and Data (CDR) Recovery
      7. 8.3.7  Internal Eye Opening Monitor (EOM)
      8. 8.3.8  Output Function Control
      9. 8.3.9  Output Driver Control
        1. 8.3.9.1 Line-Side Output Cable Driver (SDI_IO+ in CD mode, SDI_OUT+ in EQ or CD mode)
          1. 8.3.9.1.1 Output Amplitude (VOD)
          2. 8.3.9.1.2 Output Pre-Emphasis
          3. 8.3.9.1.3 Output Slew Rate
          4. 8.3.9.1.4 Output Polarity Inversion
        2. 8.3.9.2 Host-Side 100-Ω Output Driver (OUT0± in EQ or CD mode)
      10. 8.3.10 Status Indicators and Interrupts
        1. 8.3.10.1 LOCK_N (Lock Indicator)
        2. 8.3.10.2 CD_N (Carrier Detect)
        3. 8.3.10.3 INT_N (Interrupt)
      11. 8.3.11 Additional Programmability
        1. 8.3.11.1 Cable EQ Index (CEI)
        2. 8.3.11.2 Digital MUTEREF
    4. 8.4 Device Functional Modes
      1. 8.4.1 System Management Bus (SMBus) Mode
        1. 8.4.1.1 SMBus Read and Write Transaction
          1. 8.4.1.1.1 SMBus Write Operation Format
          2. 8.4.1.1.2 SMBus Read Operation Format
      2. 8.4.2 Serial Peripheral Interface (SPI) Mode
        1. 8.4.2.1 SPI Read and Write Transactions
        2. 8.4.2.2 SPI Write Transaction Format
        3. 8.4.2.3 SPI Read Transaction Format
        4. 8.4.2.4 SPI Daisy Chain
    5. 8.5 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 SMPTE Requirements and Specifications
      2. 9.1.2 Low-Power Optimization in CD Mode
      3. 9.1.3 Optimized Loop Bandwidth Settings for Arria 10 FPGA Applications
    2. 9.2 Typical Applications
      1. 9.2.1 Bidirectional I/O
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Cable Equalizer With Loop-Through
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Stack-Up and Ground References
      2. 11.1.2 High-Speed PCB Trace Routing and Coupling
        1. 11.1.2.1 SDI_IO± and SDI_OUT±:
        2. 11.1.2.2 IN0± and OUT0±:
      3. 11.1.3 Anti-Pads
      4. 11.1.4 BNC Connector Layout and Routing
      5. 11.1.5 Power Supply and Ground Connections
      6. 11.1.6 Footprint Recommendations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

9.2.1.3 Application Curves

Depending on operation in EQ or CD mode, the LMH1297 performance was measured with the test setups shown in Figure 9-3 and Figure 9-4.

GUID-663EFB69-857A-4E38-AAD6-F53FD55E7B5B-low.gifFigure 9-3 Test Setup for LMH1297 in EQ Mode
GUID-84F4A076-80D2-4F7A-BA45-32C6B82DBF5C-low.gifFigure 9-4 Test Setup for LMH1297 in CD Mode

The eye diagrams in this subsection show how the LMH1297 improves overall signal integrity in the data path for 75-Ω coax at SDI_IO+ when operating in EQ mode and 100-Ω differential FR4 PCB trace at IN0± when operating in CD mode.

GUID-BC1797FE-C669-402C-B976-7CE3C74A4471-low.png
EQ mode, measured at OUT0± HOST_EQ0 = F, SDI_OUT_SEL = H, OUT_CTRL = F
Figure 9-5 11.88 Gbps, CC = 75-m Belden 1694A, Reclocked
GUID-B397D0CF-249E-4805-9683-38671D217EDA-low.png
EQ mode, measured at OUT0± HOST_EQ0 = F, SDI_OUT_SEL = H, OUT_CTRL = F
Figure 9-7 5.94 Gbps, CC = 120-m Belden 1694A, Reclocked
GUID-E3BA11CF-33EA-4F1E-B4CE-3A75F2848036-low.png
EQ mode, measured at OUT0± HOST_EQ0 = F, SDI_OUT_SEL = H, OUT_CTRL = F
Figure 9-9 2.97 Gbps, CC = 200-m Belden 1694A, Reclocked
GUID-15A83C18-2E04-43E9-A742-9D6E6104C368-low.png
EQ mode, measured at OUT0± HOST_EQ0 = F, SDI_OUT_SEL = H, OUT_CTRL = F
Figure 9-11 1.485 Gbps, CC = 300-m Belden 1694A, Reclocked
GUID-0900F8C0-6D27-416D-9275-F8EDE5B8D30A-low.png
EQ mode, measured at OUT0± HOST_EQ0 = F, SDI_OUT_SEL = H, OUT_CTRL = F
Figure 9-13 270 Mbps, CC = 600-m Belden 1694A, Reclocked
GUID-EFED0C7D-8820-4EEC-AA2C-B792B5809C90-low.png
CD mode, measured at SDI_IO+ HOST_EQ0 = F, SDI_OUT_SEL = H, OUT_CTRL = F
Figure 9-6 11.88 Gbps, TL = 20" FR4, Reclocked
GUID-FA5E6F10-C12B-45A3-A1C6-724E232B45E7-low.png
CD mode, measured at SDI_IO+ HOST_EQ0 = F, SDI_OUT_SEL = H, OUT_CTRL = F
Figure 9-8 5.94 Gbps, TL = 20" FR4, Reclocked
GUID-BB90BAA6-944A-4C64-B30B-E53D052CFFEB-low.png
CD mode, measured at SDI_IO+ HOST_EQ0 = F, SDI_OUT_SEL = H, OUT_CTRL = F
Figure 9-10 2.97 Gbps, TL = 20" FR4, Reclocked
GUID-0912852B-0B80-4E29-A4BF-74FA93403DC3-low.png
CD mode, measured at SDI_IO+ HOST_EQ0 = F, SDI_OUT_SEL = H, OUT_CTRL = F
Figure 9-12 1.485 Gbps, TL = 20" FR4, Reclocked
GUID-1CE9041D-0798-434A-BD16-FAA0B0DF9476-low.png
CD mode, measured at SDI_IO+ HOST_EQ0 = F, SDI_OUT_SEL = H, OUT_CTRL = F
Figure 9-14 270 Mbps, TL = 20" FR4, Reclocked