JAJSHU6C January   2011  – August 2019 DRV632

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      簡略ブロック図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Operating Characteristics
    7. 8.7 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Line Driver Amplifiers
      2. 10.3.2 Charge-Pump Flying Capacitor and PVSS Capacitor
      3. 10.3.3 Decoupling Capacitors
      4. 10.3.4 Gain-Setting Resistor Ranges
      5. 10.3.5 Input-Blocking Capacitors
      6. 10.3.6 DRV632 UVP Operation
      7. 10.3.7 External Undervoltage Detection
    4. 10.4 Device Functional Modes
      1. 10.4.1 Using the DRV632 as a Second-Order Filter
      2. 10.4.2 Mute Mode
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Charge-Pump Flying, PVSS and Decoupling Capacitors
        2. 11.2.2.2 Second-Order Active Low-Pass Filters
        3. 11.2.2.3 UVP Resistor Divider
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 Gain-Setting Resistors
    2. 13.2 Layout Example
  14. 14デバイスおよびドキュメントのサポート
    1. 14.1 デバイス・サポート
      1. 14.1.1 開発サポート
    2. 14.2 コミュニティ・リソース
    3. 14.3 商標
    4. 14.4 静電気放電に関する注意事項
    5. 14.5 Glossary
  15. 15メカニカル、パッケージ、および注文情報

8.5 Electrical Characteristics

TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|VOS| Output offset voltage VDD = 3.3 V 0.5 1 mV
PSRR Power-supply rejection ratio 80 dB
VOH High-level output voltage VDD = 3.3 V 3.1 V
VOL Low-level output voltage VDD = 3.3 V –3.05 V
VUVP_EX External UVP detect voltage 1.25 V
VUVP_EX_HYSTERESIS External UVP detect hysteresis current 5 µA
fCP Charge pump switching frequency 200 300 400 kHz
|IIH| High-level input current, Mute VDD = 3.3 V, VIH = VDD 1 µA
|IIL| Low-level input current, Mute VDD = 3.3 V, VIL = 0 V 1 µA
IDD Supply current VDD = 3.3 V, no load, Mute = VDD 5 14 25 mA
VDD = 3.3 V, no load, Mute = GND, disabled 14