JAJSHU7D August   2019  – April 2021 THS6222

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: VS = 12 V
    6. 6.6 Electrical Characteristics: VS = 32 V
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics: VS = 12 V
    9. 6.9 Typical Characteristics: VS = 32 V
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Common-Mode Buffer
      2. 7.3.2 Thermal Protection and Package Power Dissipation
      3. 7.3.3 Output Voltage and Current Drive
      4. 7.3.4 Breakdown Supply Voltage
      5. 7.3.5 Surge Test Results
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Broadband PLC Line Driving
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 What to Do and What Not to Do
      1. 8.3.1 Do
      2. 8.3.2 Do Not
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Wafer and Die Information
    3. 10.3 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

NC = no internal connection.
Figure 5-1 RHF Package
24-Pin VQFN With Exposed Thermal Pad
Top View
Figure 5-2 RGT Package
16-Pin VQFN With Exposed Thermal Pad
Top View
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME RHF RGT
BIAS-1(2) 23 15 I Bias mode control, LSB
BIAS-2(2) 24 16 I Bias mode control, MSB
D1_IN– 19 11 I Amplifier D1 inverting input
D2_IN– 18 10 I Amplifier D2 inverting input
D1_IN+ 1 1 I Amplifier D1 noninverting input
D2_IN+ 2 2 I Amplifier D2 noninverting input
D1_OUT 20 12 O Amplifier D1 output
D2_OUT 17 9 O Amplifier D2 output
DGND(3) 3 3 I Ground reference for bias control pins
IADJ 4 4 I Bias current adjustment pin
NC 6-16 6 — No internal connection
VCM 5 5 O Common-mode buffer output
VS– 22 7, 14 P Negative power-supply connection
VS+ 21 8, 13 P Positive power-supply connection
Thermal Pad P Electrically connected to die substrate and VS–. Connect to VS– on the printed circuit board (PCB) for best performance.
(1) I = input, O = output, and P = power,
(2) The THS6222 defaults to the shutdown (disable) state if a signal is not present on the bias pins.
(3) The DGND pin ranges from VS– to (VS+ – 5 V).
GUID-AF074810-0607-4C02-8F64-B9EDE243554B-low.gif Figure 5-3 YS Die
19-Pad Wafer Sale
Top View
Bond Pad Functions
PAD Type(1) DESCRIPTION
NAME NO.
BIAS-1(2) 18 I Bias mode parallel control, LSB
BIAS-2(2) 19 I Bias mode parallel control, MSB
D1_IN– 11 I Amplifier D1 inverting input
D2_IN– 10 I Amplifier D2 inverting input
D1_IN+ 1 I Amplifier D1 noninverting input
D2_IN+ 2 I Amplifier D2 noninverting input
D1_OUT 13 O Amplifier D1 output (must be used for D1 output)
D1_OUT (OPT) 12 O Optional amplifier D1 output (pad can be left unconnected or connected to pad 13)
D2_OUT 8 O Amplifier D2 output (must be used for D2 output)
D2_OUT (OPT) 9 O Optional amplifier D2 output (can be left unconnected or connected to pad 8)
DGND(3) 3 I Ground reference for bias control pins
IADJ 4 I Bias current adjustment pin
VCM 5 O Common-mode buffer output
VS– 6, 16, 17 P Negative power-supply connection
VS+ 7, 14, 15 P Positive power-supply connection
Backside — — Must be connected to the lowest voltage potential on the die (generally VS–)
(1) I = input, O = output, and P = power.
(2) The THS6222 defaults to the shutdown (disable) state if a signal is not present on the bias pins.
(3) The DGND pin ranges from VS– to (VS+ – 5 V).