JAJSHU7D August   2019  – April 2021 THS6222

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: VS = 12 V
    6. 6.6 Electrical Characteristics: VS = 32 V
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics: VS = 12 V
    9. 6.9 Typical Characteristics: VS = 32 V
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Common-Mode Buffer
      2. 7.3.2 Thermal Protection and Package Power Dissipation
      3. 7.3.3 Output Voltage and Current Drive
      4. 7.3.4 Breakdown Supply Voltage
      5. 7.3.5 Surge Test Results
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Broadband PLC Line Driving
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 What to Do and What Not to Do
      1. 8.3.1 Do
      2. 8.3.2 Do Not
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Wafer and Die Information
    3. 10.3 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

10.2 Wafer and Die Information

Table 10-1 lists wafer and bond pad information for the YSpackage.

Table 10-1 Wafer and Bond Pad Information
WAFER BACKSIDE FINISHWAFER THICKNESSBACKSIDE POTENTIALBOND PAD METALLIZATIONBOND PAD DIMENSIONS (X × Y)
Silicon without backgrind25 milsMust be connected to the lowest voltage potential on the die (generally VS–)Al76.0 µm × 76.0 µm
GUID-03CB5C23-FD81-41DC-8D12-DAE2CFF22883-low.gif
All dimensions are in micrometers (µm).
Figure 10-1 Die Dimensions

Table 10-2 lists the bond pad locations for the YS package. All dimensions are in micrometers (µm).

Table 10-2 Bond Pad Locations
PAD NUMBERPAD NAMEX MINY MINX MAXY MAXDESCRIPTION
1D1_IN+71.050878.875147.050954.875Amplifier D1 noninverting input
2D2_IN+71.050525.125147.050601.125Amplifier D2 noninverting input
3DGND71.050384.025147.050460.025Ground reference for bias control pins
4IADJ71.050267.025147.050343.025Bias current adjustment pin
5VCM71.050150.025147.050226.025Common-mode buffer output
6VS–209.17585.925285.175161.925Negative power-supply connection
7VS+1007.47595.5001083.475171.500Positive power-supply connection
8D2_OUT1007.475222.5001083.475298.500Amplifier D2 output (must be used for D2 output)
9D2_OUT (OPT)1007.475369.9001083.475445.900Optional amplifier D2 output (can be left unconnected or connected to pad 8)
10D2_IN–1007.475487.3751083.475563.375Amplifier D2 inverting input
11D1_IN–1007.450919.3751083.450995.375Amplifier D1 inverting input
12D1_OUT (OPT)1007.4751034.1001083.4751110.100Optional amplifier D1 output (pad can be left unconnected or connected to pad 13)
13D1_OUT1007.4751181.5001083.4751257.500Amplifier D1 output (must be used for D1 output)
14VS+851.6751417.950927.6751493.950Positive power-supply connection
15VS+718.9001417.950794.9001493.950Positive power-supply connection
16VS–557.3751417.950633.3751493.950Negative power-supply connection
17VS–424.6001417.950500.6001493.950Negative power-supply connection
18BIAS-1293.0751417.750369.0751493.750Bias mode parallel control, LSB
19BIAS-2159.2501417.750235.2501493.750Bias mode parallel control, MSB