JAJSHV6B
August 2019 – June 2022
TLIN1028-Q1
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
概要 (続き)
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
ESD Ratings, IEC Specification
7.4
Recommended Operating Conditions
7.5
Thermal Information
7.6
Power Supply Characteristics
7.7
Electrical Charateristics
7.8
AC Switching Characteristics
7.9
Typical Characteristics
8
Parameter Measurement Information
8.1
Test Circuit: Diagrams and Waveforms
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
LIN Pin
9.3.1.1
LIN Transmitter Characteristics
9.3.1.2
LIN Receiver Characteristics
9.3.1.2.1
Termination
9.3.2
TXD (Transmit Input)
9.3.3
RXD (Receive Output)
9.3.4
VSUP (Supply Voltage)
9.3.5
GND (Ground)
9.3.6
EN (Enable Input)
9.3.7
nRST (Reset Output)
9.3.8
VCC (Supply Output)
9.3.9
Protection Features
9.3.9.1
TXD Dominant Time Out (DTO)
9.3.9.2
Bus Stuck Dominant System Fault: False Wake Up Lockout
9.3.9.3
Thermal Shutdown
9.3.9.4
Under Voltage on VSUP
9.3.9.5
Unpowered Device and LIN Bus
9.4
Device Functional Modes
9.4.1
Normal Mode
9.4.2
Sleep Mode
9.4.3
Standby Mode
9.4.4
Wake-Up Events
9.4.4.1
Wake-Up Request (RXD)
9.4.5
Mode Transitions
9.4.6
Voltage Regulator
9.4.6.1
VCC
9.4.6.2
Output Capacitance Selection
9.4.6.3
Low-Voltage Tracking
9.4.6.4
Power Supply Recommendation
10
Application and Implementation
10.1
Application Information
10.2
Typical Application
10.2.1
Design Requirements
10.2.1.1
Normal Mode Application Note
10.2.1.2
TXD Dominant State Timeout Application Note
10.2.1.3
Brownout
10.2.2
Detailed Design Procedures
10.2.3
Application Curves
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
13
Device and Documentation Support
13.1
Documentation Support
13.1.1
Related Documentation
13.2
Related Links
13.3
Receiving Notification of Documentation Updates
13.4
サポート・リソース
13.5
Trademarks
13.6
Electrostatic Discharge Caution
13.7
Glossary
14
Mechanical, Packaging, and Orderable Information
8.1
Test Circuit: Diagrams and Waveforms
Figure 8-1
Test System: Operating Voltage Range with RX and TX Access
Figure 8-2
RX Response: Operating Voltage Range
Figure 8-3
LIN Bus Input Signal
Figure 8-4
LIN Receiver Test with RX access
Figure 8-5
V
SUP_NON_OP
Test Circuit
Figure 8-6
Test Circuit for I
BUS_LIM
at Dominant State (Driver on)
Figure 8-7
Test Circuit for I
BUS_PAS_dom
; TXD = Recessive State V
BUS
= 0 V
Figure 8-8
Test Circuit for I
BUS_PAS_rec
Figure 8-9
Test Circuit for I
BUS_NO_GND
Loss of GND
Figure 8-10
Test Circuit for I
BUS_NO_BAT
Loss of Battery
Figure 8-11
Test Circuit Slope Control and Duty Cycle
Figure 8-12
Definition of Bus Timing
Figure 8-13
Propagation Delay Test Circuit
Figure 8-14
Propagation Delay
Figure 8-15
Mode Transitions
Figure 8-16
Wakeup Through EN
Figure 8-17
Wakeup through LIN
Figure 8-18
Test Circuit for AC Characteristics