JAJSHV6 データシート

JAJSHV6B August 2019 – June 2022 TLIN1028-Q1

PRODUCTION DATA

8.1 Test Circuit: Diagrams and Waveforms

Figure 8-1 Test System: Operating Voltage Range with RX and TX Access

Figure 8-2 RX Response: Operating Voltage Range

Figure 8-3 LIN Bus Input Signal

Figure 8-4 LIN Receiver Test with RX access

Figure 8-5 V_{SUP_NON_OP} Test Circuit

Figure 8-6 Test Circuit for I_{BUS_LIM} at Dominant State (Driver on)

Figure 8-7 Test Circuit for I_{BUS_PAS_dom}; TXD = Recessive State V_BUS = 0 V

Figure 8-8 Test Circuit for I_{BUS_PAS_rec}

Figure 8-9 Test Circuit for I_{BUS_NO_GND} Loss of GND

Figure 8-10 Test Circuit for I_{BUS_NO_BAT} Loss of Battery

Figure 8-11 Test Circuit Slope Control and Duty Cycle

Figure 8-12 Definition of Bus Timing

Figure 8-13 Propagation Delay Test Circuit

Figure 8-14 Propagation Delay

Figure 8-15 Mode Transitions

Figure 8-16 Wakeup Through EN

Figure 8-17 Wakeup through LIN

Figure 8-18 Test Circuit for AC Characteristics