JAJSI27A October   2019  – December 2019 DAC11001A , DAC81001 , DAC91001

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      機能ブロック図
      2.      高精度の制御ループ回路
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1      Absolute Maximum Ratings
    2. 8.2      ESD Ratings
    3. 8.3      Recommended Operating Conditions
    4. 8.4      Thermal Information Package
    5. 8.5      Electrical Characteristics
    6. Table 1. Timing Requirements: Write, 4.5 V ≤ DVDD ≤ 5.5 V
    7. Table 2. Timing Requirements: Write, 2.7 V ≤ DVDD < 4.5 V
    8. Table 3. Timing Requirements: Read and Daisy-Chain Write, 4.5 V ≤ DVDD ≤ 5.5 V
    9. Table 4. Timing Requirements: Read and Daisy-Chain Write, 2.7 V ≤ DVDD < 4.5 V
    10. 8.6      Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Digital-to-Analog Converter Architecture
      2. 9.3.2 External Reference
      3. 9.3.3 Output Buffers
      4. 9.3.4 Internal Power-On Reset (POR)
      5. 9.3.5 Temperature Drift and Calibration
      6. 9.3.6 DAC Output Deglitch Circuit
    4. 9.4 Device Functional Modes
      1. 9.4.1 Fast-Settling Mode and THD
      2. 9.4.2 DAC Update Rate Mode
    5. 9.5 Programming
      1. 9.5.1 Daisy-Chain Operation
      2. 9.5.2 CLR Pin Functionality and Software Clear
      3. 9.5.3 Output Update (Synchronous and Asynchronous)
        1. 9.5.3.1 Synchronous Update
        2. 9.5.3.2 Asynchronous Update
      4. 9.5.4 Software Reset Mode
    6. 9.6 Register Map
      1. 9.6.1 NOP Register (address = 00h) [reset = 0x000000h]
        1. Table 9. NOP Register Field Descriptions
      2. 9.6.2 DAC-DATA Register (address = 01h) [reset = 0x000000h]
        1. Table 10. DAC-DATA Register Field Descriptions
      3. 9.6.3 CONFIG1 Register (address = 02h) [reset = 004C80h for bits [23:0]]
        1. Table 11. CONFIG1 Register Field Descriptions
      4. 9.6.4 DAC-CLEAR-DATA Register (address = 03h) [reset = 000000h for bits [23:0]]
        1. Table 12. DAC-CLEAR-DATA Register Field Descriptions
      5. 9.6.5 TRIGGER Register (address = 04h) [reset = 000000h for bits [23:0]]
        1. Table 13. TRIGGER Register Field Descriptions
      6. 9.6.6 STATUS Register (address = 05h) [reset = 000000h for bits [23:0]]
        1. Table 14. STATUS Register Field Descriptions
      7. 9.6.7 CONFIG2 Register (address = 06h) [reset = 000040h for bits [23:0]]
        1. Table 15. CONFIG2 Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Source Measure Unit (SMU)
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Battery Test Equipment (BTE)
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
      3. 10.2.3 High-Precision Control Loop
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curves
      4. 10.2.4 Arbitrary Waveform Generation (AWG)
        1. 10.2.4.1 Design Requirements
        2. 10.2.4.2 Detailed Design Procedure
        3. 10.2.4.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Interfacing to a Processor
      2. 10.3.2 Interfacing to a Low-Jitter LDAC Source
      3. 10.3.3 Embedded Resistor Configurations
        1. 10.3.3.1 Minimizing Bias Current Mismatch
        2. 10.3.3.2 2x Gain configuration
        3. 10.3.3.3 Generating Negative Reference
    4. 10.4 What to Do and What Not to Do
      1. 10.4.1 What to Do
      2. 10.4.2 What Not to Do
    5. 10.5 Initialization Set Up
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Sequencing
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 開発サポート
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 関連リンク
    4. 13.4 ドキュメントの更新通知を受け取る方法
    5. 13.5 サポート・リソース
    6. 13.6 商標
    7. 13.7 静電気放電に関する注意事項
    8. 13.8 Glossary
  14. 14メカニカル、パッケージ、および注文情報

8.5 Electrical Characteristics

at TA = –40°C to +125°C, VCC = +15 V, VSS = –15 V, AVDD = 5.5 V, DVDD = 3.3 V, IOVDD = 1.8 V, see note(1) for VREFPF and VREFNF, 20-bit orderable used, OUT pin buffered with unity gain OPA827, ROFS, RCM, RFB unconnected, and all typical specifications at TA = 25°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE
Resolution DAC11001A 20 Bits
DAC91001 18
DAC81001 16
INL Relative accuracy(2) –4 4 LSB
Relative accuracy(2)(3)(5) –2.6 2.6
Relative accuracy(2)(5) DACx1001A TA = 25°C –2 2
Relative accuracy drift over time(2) TA = 25°C, 1000 hrs 0.1 LSB
DNL Differential nonlinearity(2)(3) –1 1 LSB
Zero code error(5) TA = 0°C to 70°C, code 0d into DAC, unipolar ranges only –4 4 LSB
TA = –40°C to +125°C, code 0d into DAC, unipolar ranges only –4 4
TA = 25°C, unipolar ranges only ±2
Zero code error temperature coefficient TA = 0°C to 70°C, code 0d into DAC, unipolar ranges only ±0.04 ppm FSR/°C
TA = –40°C to +125°C, code 0d into DAC, unipolar ranges only ±0.04
Gain error(2)(5) TA = 0°C to 70°C –8 8 ppm of FSR
TA = 0°C to 70°C, VREFPF = 3 V, VREFNF = –10 V –8 8
TA = –40°C to +125°C –10 10
TA = 25°C ±2
Gain error temperature coefficient TA = 0°C to 70°C ±0.04 ppm FSR/°C
TA = 0°C to 70°C, VREFPF = 3 V, VREFNF = –10 V ±0.04
TA = –40°C to +125°C ±0.04
Positive full-scale error(5) TA = 0°C to 70°C, code 1048575d into DAC –8 8 LSB
TA = 0°C to 70°C, code 1048575d into DAC, VREFPF = 3 V, VREFNF = –10 V –6 6
TA = –40°C to +125°C, code 1048575d into DAC –10 10
TA = 25°C ±2
Full-scale error temperature coefficient TA = 0°C to 70°C ±0.04 ppm FSR/°C
TA = 0°C to 70°C, VREFPF = 3 V, VREFNF = –10 V ±0.04
TA = –40°C to +125°C ±0.04
OUTPUT CHARACTERISTICS
Headroom From VREFPF to VCC 3 V
Footroom From VREFNF to VSS 3 V
DC impedance From ROFS to RCM 5 kΩ
From RCM to RFB 5
ZO DC output impedance 2.5 kΩ
Power supply rejection ratio (dc) TA = 25°C, VCC = 15 V ± 20%,
VSS = –15 V		 1.5 µV/V
TA = 25°C, VCC = 15 V,
VSS = –15 V ± 20%		 1
VOLTAGE REFERENCE INPUT
Reference input impedance (REFPF) DAC at midscale, VREFPF = 10 V, VREFNF = 0 V 5.5 kΩ
Reference input impedance (REFNF) DAC at midscale, VREFPF = 10 V, VREFNF = 0 V 7
DYNAMIC PERFORMANCE
ts Output voltage settling time(4) VREFPF = 10 V, VREFNF = 0 V,
full-scale settling to 0.1%FSR		 1 µs
VREFPF = 10 V, VREFNF = 0 V,
full-scale settling to ±1 LSB		 2.5
VREFPF = 10 V, VREFNF = 0 V,
1-mV step settling to ±1 LSB		 2.5
SR Slew rate VREFPF = 10 V, VREFNF = 0 V, full-scale step, measured at OUT pin 50 V/µs
Power-on glitch magnitude Measured at unbuffered DAC voltage output, VREFPF = 10 V, VREFNF = 0 V –0.2 V
Vn Output noise 0.1-Hz to 10-Hz, DAC at midscale, VREFPF = 10 V, VREFNF = 0 V 0.4 µVpp
100-kHz bandwidth, DAC at midscale, VREFPF = 10 V, VREFNF = 0 V 3 µVrms
Output noise density Measured at 1 kHz, 10 kHz, 100 kHz, DAC at mid scale, VREFPF = 10 V, VREFNF = 0 V 7 nV/√Hz
SFDR Spurious free dynamic range DAC update rate = 400 kHz, fOUT = 1 kHz, VOUTPP = 0 V to 10 V –105 dB
DAC update rate = 400 kHz, fOUT = 1 kHz, VOUTPP = 3 V to –10 V –105 dB
THD Total harmonic distortion DAC update rate = 400 kHz, fOUT = 1 kHz, VOUTPP = 0 V to 10 V –105 dB
DAC update rate = 400 kHz, fOUT = 1 kHz, VOUTPP = 3 V to –10 V –105 dB
Power supply rejection ratio (ac) 200-mV 50-Hz or 60-Hz sine wave superimposed on VSS, VCC = 15 V 95 dB
200-mV 50 Hz or 60 Hz sine wave superimposed on VCC, VSS = –15 V 95 dB
Code change glitch impulse ±1 LSB change around mid code (including feedthrough), VREFPF = 10 V, VREFNF = 0 V, measured at output of buffer op amp 1 nV-s
Code change glitch impulse magnitude ±1 LSB change around mid code (including feedthrough), VREFPF = 10 V, VREFNF = 0  V, measured at output of buffer op amp 5 mV
Reference feedthrough VREFPF = 10 V ± 10%, VREFNF = 0 V, frequency = 100 Hz, DAC at zero scale –90 dB
Reference feedthrough VREFNF = –10 V ± 10%, VREFPF = 10 V, frequency = 100 Hz, DAC at full scale –90 dB
Digital feedthrough At SCLK = 1 MHz, DAC output static at midscale, 10-V range 1 nV-s
DIGITAL INPUTS
Hysteresis voltage 0.4 V
Input current ±5 µA
Pin capacitance Per pin 10 pF
DIGITAL OUTPUTS
VOL Output low voltage sinking 200 µA 0.4 V
VOH Output high voltage sourcing 200 µA IOVDD – 0.5 V
High impedance leakage ±5 µA
High impedance output capacitance 10 pF
POWER
IAVDD Current flowing into AVDD VREFPF = 10 V, VREFNF = 0 V, midscale code 1.5 mA
IVCC Current flowing into VCC VREFPF = 10 V, VREFNF = 0 V, midscale code 7 mA
IVSS Current flowing into VSS VREFPF = 10 V, VREFNF = 0 V, midscale code 7 mA
IDVDD Current flowing into DVDD VREFPF = 10 V, VREFNF = 0 V, midscale code 0.5 mA
IIOVDD Current flowing into IOVDD VREFPF = 10 V, VREFNF = 0 V, midscale code, all digital input pins static at IOVDD 0.1 mA
IREFPF Reference input current (VREFPF) VREFPF = 10 V, VREFNF = 0 V, midscale code 5 mA
IREFNF Reference input current (VREFNF) VREFPF = 10 V, VREFNF = 0 V, midscale code 5 mA
(1) Specified for the following pairs: VREFPF = 5 V and VREFNF = 0 V; VREFPF = 10 V and VREFNF = 0 V; VREFPF = +5 V and VREFNF = –5 V; VREFPF = +10 V and VREFNF = –10 V.
(2) Calculated between code 0d to 1048575d.
(3) With device temperature calibration mode enabled and used.
(4) Adaptive TnH mode. TnH action is disabled for large code steps. For small steps, TnH action happens with a hold time of 1.2µs.
(5) Specified by design, not production tested.