JAJSI27A October   2019  – December 2019 DAC11001A , DAC81001 , DAC91001

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      機能ブロック図
      2.      高精度の制御ループ回路
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1      Absolute Maximum Ratings
    2. 8.2      ESD Ratings
    3. 8.3      Recommended Operating Conditions
    4. 8.4      Thermal Information Package
    5. 8.5      Electrical Characteristics
    6. Table 1. Timing Requirements: Write, 4.5 V ≤ DVDD ≤ 5.5 V
    7. Table 2. Timing Requirements: Write, 2.7 V ≤ DVDD < 4.5 V
    8. Table 3. Timing Requirements: Read and Daisy-Chain Write, 4.5 V ≤ DVDD ≤ 5.5 V
    9. Table 4. Timing Requirements: Read and Daisy-Chain Write, 2.7 V ≤ DVDD < 4.5 V
    10. 8.6      Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Digital-to-Analog Converter Architecture
      2. 9.3.2 External Reference
      3. 9.3.3 Output Buffers
      4. 9.3.4 Internal Power-On Reset (POR)
      5. 9.3.5 Temperature Drift and Calibration
      6. 9.3.6 DAC Output Deglitch Circuit
    4. 9.4 Device Functional Modes
      1. 9.4.1 Fast-Settling Mode and THD
      2. 9.4.2 DAC Update Rate Mode
    5. 9.5 Programming
      1. 9.5.1 Daisy-Chain Operation
      2. 9.5.2 CLR Pin Functionality and Software Clear
      3. 9.5.3 Output Update (Synchronous and Asynchronous)
        1. 9.5.3.1 Synchronous Update
        2. 9.5.3.2 Asynchronous Update
      4. 9.5.4 Software Reset Mode
    6. 9.6 Register Map
      1. 9.6.1 NOP Register (address = 00h) [reset = 0x000000h]
        1. Table 9. NOP Register Field Descriptions
      2. 9.6.2 DAC-DATA Register (address = 01h) [reset = 0x000000h]
        1. Table 10. DAC-DATA Register Field Descriptions
      3. 9.6.3 CONFIG1 Register (address = 02h) [reset = 004C80h for bits [23:0]]
        1. Table 11. CONFIG1 Register Field Descriptions
      4. 9.6.4 DAC-CLEAR-DATA Register (address = 03h) [reset = 000000h for bits [23:0]]
        1. Table 12. DAC-CLEAR-DATA Register Field Descriptions
      5. 9.6.5 TRIGGER Register (address = 04h) [reset = 000000h for bits [23:0]]
        1. Table 13. TRIGGER Register Field Descriptions
      6. 9.6.6 STATUS Register (address = 05h) [reset = 000000h for bits [23:0]]
        1. Table 14. STATUS Register Field Descriptions
      7. 9.6.7 CONFIG2 Register (address = 06h) [reset = 000040h for bits [23:0]]
        1. Table 15. CONFIG2 Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Source Measure Unit (SMU)
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Battery Test Equipment (BTE)
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
      3. 10.2.3 High-Precision Control Loop
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curves
      4. 10.2.4 Arbitrary Waveform Generation (AWG)
        1. 10.2.4.1 Design Requirements
        2. 10.2.4.2 Detailed Design Procedure
        3. 10.2.4.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Interfacing to a Processor
      2. 10.3.2 Interfacing to a Low-Jitter LDAC Source
      3. 10.3.3 Embedded Resistor Configurations
        1. 10.3.3.1 Minimizing Bias Current Mismatch
        2. 10.3.3.2 2x Gain configuration
        3. 10.3.3.3 Generating Negative Reference
    4. 10.4 What to Do and What Not to Do
      1. 10.4.1 What to Do
      2. 10.4.2 What Not to Do
    5. 10.5 Initialization Set Up
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Sequencing
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 開発サポート
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 関連リンク
    4. 13.4 ドキュメントの更新通知を受け取る方法
    5. 13.5 サポート・リソース
    6. 13.6 商標
    7. 13.7 静電気放電に関する注意事項
    8. 13.8 Glossary
  14. 14メカニカル、パッケージ、および注文情報

9.6.3 CONFIG1 Register (address = 02h) [reset = 004C80h for bits [23:0]]

Figure 51. CONFIG1 Register Format
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Read/Write Address EN_
TMP_
CAL		 0h TNH_MASK 0h
R/W W R/W W R/W W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0h LDAC
MODE		 FSDO ENALMP DSDO FSET VREFVAL 0h PDN 0h
W R/W W R/W W

Table 11. CONFIG1 Register Field Descriptions

Bit Field Type Reset Description
31 Read/Write R/W N/A Read when set to 1 or write when set to 0
30:24 Address W N/A 02h
23 EN_TMP_CAL R/W 0h Enables and disables the temperature calibration feature
0 : Temperature calibration feature disabled (default)
1 : Temperature calibration feature enabled
22:20 0h W N/A N/A
19-18 TNH_MASK R/W 0h Mask track and hold (TNH) circuit. This bit is writable only when FSET = 0 [fast-settling mode] and DIS_TNH = 0 [track-and-hold enabled]
00: TNH masked for code jump > 2^14 (default)
01: TNH masked for code jump > 2^15
10: TNH masked for code jump > 2^13
11: TNH masked for code jump > 2^12
17:15 0h W N/A N/A
14 LDACMODE R/W 1 Synchronous or asynchronous mode select bit
0 : DAC output updated on SYNC rising edge
1 : DAC updated on LDAC falling edge (default)
13 FSDO R/W 0h Enable Fast SDO
0 : Fast SDO disabled (Default)
1 : Fast SDO enabled
12 ENALMP R/W 0h Enable ALARM pin to be pulled low, end of temperature calibration cycle
0 : No alarm on the ALARM pin
1 : Indicates end of temperature calibration cycle. ALARM pin pulled low.
11 DSDO R/W 1h Enable SDO (for readback and daisy-chain)
1 : SDO enabled (default)
0 : SDO disabled
10 FSET R/W 1h Fast-settling vs enhanced THD mode
0 : Fast settling
1 : Enhanced THD (default)
9:6 VREFVAL R/W 2h Reference span value bits
0000: Invalid
0001: Invalid
0010: Reference span = 5 V ± 1.25 V (default)
0011: Reference span = 7.5 V ± 1.25 V
0100: Reference span = 10 V ± 1.25 V
0101: Reference span = 12.5 V ± 1.25 V
0110: Reference span = 15 V ± 1.25 V
0111: Reference span = 17.5 V ± 1.25 V
1000: Reference span = 20 V ± 1.25 V
1001: Reference span = 22.5 V ± 1.25 V
1010: Reference span = 25 V ± 1.25 V
1011: Reference span = 27.5 V± 1.25 V
1100: Reference span = 30 V ± 1.25 V
5 0 W N/A N/A
4 PDN R/W 0h Powers down and power up the DAC
0 : DAC power up (default)
1 : DAC power down
3:0 0000 R/W N/A N/A