JAJSI66A November   2019  – March 2020 TPS7A54

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      デジタル負荷の電源
      2.      RFコンポーネントの電源
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Regulation Features
        1. 8.3.1.1 DC Regulation
        2. 8.3.1.2 AC and Transient Response
      2. 8.3.2 System Start-Up Features
        1. 8.3.2.1 Programmable Soft Start (NR/SS Pin)
        2. 8.3.2.2 Internal Sequencing
          1. 8.3.2.2.1 Enable (EN)
          2. 8.3.2.2.2 Undervoltage Lockout (UVLO) Control
          3. 8.3.2.2.3 Active Discharge
        3. 8.3.2.3 Power-Good Output (PG)
      3. 8.3.3 Internal Protection Features
        1. 8.3.3.1 Foldback Current Limit (ICL)
        2. 8.3.3.2 Thermal Protection (Tsd)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Regulation
      2. 8.4.2 Disabled
      3. 8.4.3 Current Limit Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1  Recommended Capacitor Types
        1. 9.1.1.1 Input and Output Capacitor Requirements (CIN and COUT)
        2. 9.1.1.2 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
        3. 9.1.1.3 Feed-Forward Capacitor (CFF)
      2. 9.1.2  Soft Start and Inrush Current
      3. 9.1.3  Optimizing Noise and PSRR
      4. 9.1.4  Charge Pump Noise
      5. 9.1.5  Current Sharing
      6. 9.1.6  Adjustable Operation
      7. 9.1.7  Power-Good Operation
      8. 9.1.8  Undervoltage Lockout (UVLO) Operation
      9. 9.1.9  Dropout Voltage (VDO)
      10. 9.1.10 Device Behavior During Transition From Dropout Into Regulation
      11. 9.1.11 Load Transient Response
      12. 9.1.12 Reverse Current Protection Considerations
      13. 9.1.13 Power Dissipation (PD)
      14. 9.1.14 Estimating Junction Temperature
      15. 9.1.15 TPS7A54EVM Thermal Analysis
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Layout
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. 12.1.1.1 評価基板
        2. 12.1.1.2 SPICEモデル
      2. 12.1.2 デバイスの項目表記
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.