JAJSI66A November   2019  – March 2020 TPS7A54

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      デジタル負荷の電源
      2.      RFコンポーネントの電源
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Regulation Features
        1. 8.3.1.1 DC Regulation
        2. 8.3.1.2 AC and Transient Response
      2. 8.3.2 System Start-Up Features
        1. 8.3.2.1 Programmable Soft Start (NR/SS Pin)
        2. 8.3.2.2 Internal Sequencing
          1. 8.3.2.2.1 Enable (EN)
          2. 8.3.2.2.2 Undervoltage Lockout (UVLO) Control
          3. 8.3.2.2.3 Active Discharge
        3. 8.3.2.3 Power-Good Output (PG)
      3. 8.3.3 Internal Protection Features
        1. 8.3.3.1 Foldback Current Limit (ICL)
        2. 8.3.3.2 Thermal Protection (Tsd)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Regulation
      2. 8.4.2 Disabled
      3. 8.4.3 Current Limit Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1  Recommended Capacitor Types
        1. 9.1.1.1 Input and Output Capacitor Requirements (CIN and COUT)
        2. 9.1.1.2 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
        3. 9.1.1.3 Feed-Forward Capacitor (CFF)
      2. 9.1.2  Soft Start and Inrush Current
      3. 9.1.3  Optimizing Noise and PSRR
      4. 9.1.4  Charge Pump Noise
      5. 9.1.5  Current Sharing
      6. 9.1.6  Adjustable Operation
      7. 9.1.7  Power-Good Operation
      8. 9.1.8  Undervoltage Lockout (UVLO) Operation
      9. 9.1.9  Dropout Voltage (VDO)
      10. 9.1.10 Device Behavior During Transition From Dropout Into Regulation
      11. 9.1.11 Load Transient Response
      12. 9.1.12 Reverse Current Protection Considerations
      13. 9.1.13 Power Dissipation (PD)
      14. 9.1.14 Estimating Junction Temperature
      15. 9.1.15 TPS7A54EVM Thermal Analysis
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Layout
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. 12.1.1.1 評価基板
        2. 12.1.1.2 SPICEモデル
      2. 12.1.2 デバイスの項目表記
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

7.6 Typical Characteristics

at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.4 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V, COUT = 47 µF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted)
TPS7A54 D035-SBVS311-01.gif
VIN = 1.2 V, VBIAS = 5 V,
COUT = 47 µF || 10 µF || 10 µF, CNR/SS = 10 nF, CFF = 10 nF
Figure 1. PSRR vs Frequency and IOUT
TPS7A54 D037-SBVS311-03.gif
VIN = 1.4 V, IOUT = 1 A,
COUT = 47 µF || 10 µF || 10 µF, CNR/SS = 10 nF, CFF = 10 nF
Figure 3. PSRR vs Frequency and VBIAS
TPS7A54 D032-SBVS311-01.gif
VIN = VOUT + 0.4 V, VBIAS = 5.0 V, IOUT = 4 A,
COUT = 47 µF || 10 µF || 10 µF, CNR/SS = 10 nF, CFF = 10 nF
Figure 5. PSRR vs Frequency and VOUT With Bias
TPS7A54 D040-SBVS311-01.gif
VIN = VOUT + 0.4 V, VOUT = 1 V, IOUT = 4 A,
CNR/SS = 10 nF, CFF = 10 nF
Figure 7. PSRR vs Frequency and COUT
TPS7A54 Noise_vs_Vout_Iout.gif
VIN = VOUT + 0.4 V and VBIAS = 5 V for VOUT ≤ 2.2 V,
COUT = 47 µF || 10 µF || 10 µF, CNR/SS = 10 nF, CFF = 10 nF,
RMS noise BW = 10 Hz to 100 kHz
Figure 9. Output Voltage Noise vs Output Voltage
TPS7A54 Noise_vs_Vin.gif
IOUT = 1 A,
COUT = 47 µF || 10 µF || 10 µF, CNR/SS = 10 nF, CFF = 10 nF,
RMS noise BW = 10 Hz to 100 kHz
Figure 11. Output Noise vs Frequency and Input Voltage
TPS7A54 Noise_vs_Cff.gif
VIN = VOUT + 0.4 V, VBIAS = 5 V, IOUT = 4 A, sequencing with a DC/DC converter and PG, COUT = 47 µF || 10 µF || 10 µF,
CNR/SS = 10 nF, RMS noise BW = 10 Hz to 100 kHz
Figure 13. Output Noise vs Frequency and CFF
TPS7A54 Startup_Vs_Cnr.gif
VIN = 1.2 V, VOUT = 0.9 V, VBIAS = 5.0 V, IOUT = 4 A,
COUT = 47 µF || 10 µF || 10 µF, CFF = 10 nF
Figure 15. Start-Up Waveform vs Time and CNR/SS
TPS7A54 Load_trans_vs_Vout_no_bias.gif
IOUT, DC = 100 mA, COUT = 47 µF || 10 µF || 10 µF,
CNR/SS = CFF = 10 nF, slew rate = 1 A/µs
Figure 17. Load Transient vs Time and VOUT Without Bias
TPS7A54 Load_Trans_vs_preload.gif
VIN = 1.2 V, VBIAS = 5.0 V, COUT = 47 µF || 10 µF || 10 µF,
CNR/SS = CFF = 10 nF, slew rate = 1 A/µs
Figure 19. Load Transient vs Time and DC Load
(VOUT = 0.9 V)
TPS7A54 D023-sbvs311-01.gif
IOUT = 4 A, VBIAS = 5 V
Figure 21. Dropout Voltage vs Input Voltage With Bias
TPS7A54 D034-SBVS311-01.gif
VIN = 1.1 V, VBIAS = 3 V
Figure 23. Dropout Voltage vs Output Current With Bias
TPS7A54 D022-SBVS311-02.gif
VIN = 1.1 V, VBIAS = 5 V
Figure 25. Load Regulation With Bias
TPS7A54 D023-SBVS311-04.gif
VOUT = 0.8 V, VBIAS = 0 V, IOUT = 5 mA
Figure 27. Line Regulation Without Bias
TPS7A54 D015-SBVS311-02.gif
VIN = 1.1 V, IOUT = 5 mA
Figure 29. Quiescent Current vs Bias Voltage
TPS7A54 D017-SBVS311-05.gif
VIN = 1.1 V
Figure 31. Shutdown Current vs Bias Voltage
TPS7A54 D019-SBVS311-03.gif
Figure 33. VIN UVLO vs Temperature
TPS7A54 D026-SBVS311-01.gif
VIN = 1.4 V, 6.5 V
Figure 35. Enable Threshold vs Temperature
TPS7A54 D029-SBVS311-02.gif
VIN = 6.5 V
Figure 37. PG Voltage vs PG Current Sink
TPS7A54 D041-SBVS311-01.gif
VIN = 1.1 V, VBIAS = 3 V
Figure 39. Foldback Current Limit vs Temperature
TPS7A54 D036-SBVS311-02.gif
IOUT = 4 A, VBIAS = 5 V,
COUT = 47 µF || 10 µF || 10 µF, CNR/SS = 10 nF, CFF = 10 nF
Figure 2. PSRR vs Frequency and VIN With Bias
TPS7A54 D038-SBVS311-04.gif
IOUT = 1 A,
COUT = 47 µF || 10 µF || 10 µF, CNR/SS = 10 nF, CFF = 10 nF
Figure 4. PSRR vs Frequency and VIN
TPS7A54 D030-SBVS311-01.gif
IOUT = 4 A,
COUT = 47 µF || 10 µF || 10 µF, CNR/SS = 10 nF, CFF = 10 nF
Figure 6. PSRR vs Frequency and VIN for VOUT = 3.3 V
TPS7A54 D031-SBVS311-01.gif
VIN = VOUT + 0.6 V,
COUT = 47 µF || 10 µF || 10 µF, CNR/SS = 10 nF, CFF = 10 nF
Figure 8. PSRR vs Frequency and IOUT for VOUT = 5 V
TPS7A54 Noise_vs_Vout.gif
VIN = VOUT + 0.4 V and VBIAS = 5 V for VOUT ≤ 2.2 V, IOUT = 4 A,
COUT = 47 µF || 10 µF || 10 µF, CNR/SS = 10 nF, CFF = 10 nF,
RMS noise BW = 10 Hz to 100 kHz
Figure 10. Output Noise vs Frequency and VOUT
TPS7A54 Noise_vs_Cnr.gif
VIN = VOUT + 0.4 V, VBIAS = 5 V, IOUT = 4 A,
COUT = 47 µF || 10 µF || 10 µF, CFF = 10 nF,
RMS noise BW = 10 Hz to 100 kHz
Figure 12. Output Noise vs Frequency and CNR/SS
TPS7A54 Noise_vs_Cnr_Cff_5Vout.gif
VIN = 5.6 V, IOUT = 4 A,
COUT = 47 µF || 10 µF || 10 µF, CFF = 10 nF,
RMS noise BW = 10 Hz to 100 kHz
Figure 14. Output Noise at 5.0-V Output
TPS7A54 Load_trans_vs_Vout.gif
VIN = VOUT + 0.3 V, VBIAS = 5 V, IOUT, DC = 100 mA, slew rate = 1 A/µs, CNR/SS = CFF = 10 nF, COUT = 47 µF || 10 µF || 10 µF
Figure 16. Load Transient vs Time and VOUT With Bias
TPS7A54 Load_trans_vs_SR.gif
VOUT = 5 V, IOUT, DC = 100 mA, IOUT = 100 mA to 4 A,
COUT = 47 µF || 10 µF || 10 µF, CNR/SS = CFF = 10 nF
Figure 18. Load Transient vs Time and Slew Rate
TPS7A54 D022-sbvs311-01.gif
IOUT = 4 A, VBIAS = 0 V
Figure 20. Dropout Voltage vs Input Voltage Without Bias
TPS7A54 D004-SBVS311-03.gif
VIN = 1.4 V, VBIAS = 0 V
Figure 22. Dropout Voltage vs Output Current Without Bias
TPS7A54 D005-SBVS311-04.gif
VIN = 5.5 V
Figure 24. Dropout Voltage vs Output Current (High VIN)
TPS7A54 D021-SBVS311-01.gif
VIN = 1.4 V, VBIAS = 0 V
Figure 26. Load Regulation Without Bias
TPS7A54 D011-SBVS311-01.gif
VBIAS = 0 V, IOUT = 5 mA
Figure 28. Quiescent Current vs Input Voltage
TPS7A54 D016-SBVS311-04.gif
VBIAS = 0 V
Figure 30. Shutdown Current vs Input Voltage
TPS7A54 D018-SBVS311-06.gif
VBIAS = 0 V
Figure 32. NR/SS Current vs Input Voltage and Temperature
TPS7A54 D020-SBVS311-04.gif
VIN = 1.1 V
Figure 34. VBIAS UVLO vs Temperature
TPS7A54 D028-SBVS311-01.gif
Figure 36. PG Voltage vs PG Current Sink
TPS7A54 D039-SBVS311-01.gif
Figure 38. PG Threshold vs Temperature