JAJSI66A November   2019  – March 2020 TPS7A54

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      デジタル負荷の電源
      2.      RFコンポーネントの電源
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Regulation Features
        1. 8.3.1.1 DC Regulation
        2. 8.3.1.2 AC and Transient Response
      2. 8.3.2 System Start-Up Features
        1. 8.3.2.1 Programmable Soft Start (NR/SS Pin)
        2. 8.3.2.2 Internal Sequencing
          1. 8.3.2.2.1 Enable (EN)
          2. 8.3.2.2.2 Undervoltage Lockout (UVLO) Control
          3. 8.3.2.2.3 Active Discharge
        3. 8.3.2.3 Power-Good Output (PG)
      3. 8.3.3 Internal Protection Features
        1. 8.3.3.1 Foldback Current Limit (ICL)
        2. 8.3.3.2 Thermal Protection (Tsd)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Regulation
      2. 8.4.2 Disabled
      3. 8.4.3 Current Limit Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1  Recommended Capacitor Types
        1. 9.1.1.1 Input and Output Capacitor Requirements (CIN and COUT)
        2. 9.1.1.2 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
        3. 9.1.1.3 Feed-Forward Capacitor (CFF)
      2. 9.1.2  Soft Start and Inrush Current
      3. 9.1.3  Optimizing Noise and PSRR
      4. 9.1.4  Charge Pump Noise
      5. 9.1.5  Current Sharing
      6. 9.1.6  Adjustable Operation
      7. 9.1.7  Power-Good Operation
      8. 9.1.8  Undervoltage Lockout (UVLO) Operation
      9. 9.1.9  Dropout Voltage (VDO)
      10. 9.1.10 Device Behavior During Transition From Dropout Into Regulation
      11. 9.1.11 Load Transient Response
      12. 9.1.12 Reverse Current Protection Considerations
      13. 9.1.13 Power Dissipation (PD)
      14. 9.1.14 Estimating Junction Temperature
      15. 9.1.15 TPS7A54EVM Thermal Analysis
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Layout
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. 12.1.1.1 評価基板
        2. 12.1.1.2 SPICEモデル
      2. 12.1.2 デバイスの項目表記
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

9.1.3 Optimizing Noise and PSRR

Improve the ultra-low noise floor and PSRR of the device by careful selection of:

  • CNR/SS for the low-frequency range
  • CFF in the midband frequency range
  • COUT for the high-frequency range
  • VIN – VOUT for all frequencies, and
  • VBIAS at lower input voltages

A larger noise-reduction capacitor improves low-frequency PSRR by filtering any noise coupling from the input into the reference. To improve midband PSRR, use the feed-forward capacitor to place a zero-pole pair near the edge of the loop bandwidth and push out the loop bandwidth. Use larger output capacitors to improve high-frequency PSRR.

A higher input voltage improves PSRR by giving the device more headroom to respond to noise on the input. A bias rail also improves PSRR at lower input voltages because greater headroom is provided for the internal circuits.

The noise-reduction capacitor filters out low-frequency noise from the reference, and the feed-forward capacitor reduces output voltage noise by filtering out midband frequency noise. However, a large feed-forward capacitor can create new issues that are discussed in the Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator application report.

Use a large output capacitor to reduce high-frequency output voltage noise. Additionally, a bias rail or higher input voltage improves noise because greater headroom is provided for the internal circuits.

Table 4 lists the output voltage noise for the 10-Hz to 100-kHz band at a 5.0-V output for a variety of conditions with an input voltage of 5.5 V, an R1 of 12.1 kΩ, and a load current of 4 A. The 5.0-V output is used because this output is the worst-case condition for output voltage noise.

Table 4. Output Noise Voltage at a 5.0-V Output

OUTPUT VOLTAGE NOISE
(µVRMS)		 CNR/SS
(nF)		 CFF
(nF)		 COUT
(µF)
11.7 10 10 47 || 10 || 10
7.7 100 10 47 || 10 || 10
6 100 100 47 || 10 || 10
7.4 100 10 1000
5.8 100 100 1000