JAJSI73C December   2009  – December 2019 BQ24072T , BQ24075T , BQ24079T

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Options
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Undervoltage Lockout (UVLO)
      2. 9.3.2  Overvoltage Protection (OVP)
      3. 9.3.3  Dynamic Power-Path Management
      4. 9.3.4  Battery Charging
      5. 9.3.5  Charge Current Translator
      6. 9.3.6  Battery Detection and Recharge
      7. 9.3.7  Termination Disable (TD Input, BQ24072T)
      8. 9.3.8  Battery Disconnect (SYSOFF Input)
      9. 9.3.9  Dynamic Charge Timers (TMR Input)
      10. 9.3.10 Status Indicators (PGOOD, CHG)
      11. 9.3.11 Thermal Regulation and Thermal Shutdown
      12. 9.3.12 Battery Pack Temperature Monitoring
    4. 9.4 Device Functional Modes
      1. 9.4.1 Input Source Connected (Adapter or USB)
        1. 9.4.1.1 Input DPM Mode (VIN-DPM)
        2. 9.4.1.2 DPPM Mode
        3. 9.4.1.3 Battery Supplement Mode
      2. 9.4.2 Input Source Not Connected
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Using the BQ24075T, BQ24079T to Disconnect the Battery from the System
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Program the Fast Charge Current (ISET):
          2. 10.2.1.2.2 Program the Input Current Limit (ILIM):
          3. 10.2.1.2.3 Program 6.25-hour Fast-Charge Safety Timer (TMR):
          4. 10.2.1.2.4 TS Function:
          5. 10.2.1.2.5 CHG and PGOOD LED Status:
          6. 10.2.1.2.6 Processor Monitoring Status:
          7. 10.2.1.2.7 System ON/OFF (SYSOFF):
          8. 10.2.1.2.8 Selecting IN, OUT and BAT Capacitors
        3. 10.2.1.3 Application Curves
      2. 10.2.2 BQ24072T in a Host Controlled Charger Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedures
          1. 10.2.2.2.1 Termination Disable:
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power On
      1. 11.1.1 Half-Wave Adapters
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Package
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 13.2 関連リンク
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 サポート・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

9.3.1 Undervoltage Lockout (UVLO)

The BQ2407X family remains in power down mode when the input voltage at the IN pin is below the undervoltage threshold (UVLO). During the power down mode the host commands at the control inputs (CE, EN1 and EN2) are ignored. The Q1 FET connected between IN and OUT pins is off, and the status outputs, CHG and PGOOD, are high impedance. The Q2 FET that connects BAT to OUT is ON. (If SYSOFF is high, Q2 is off). During power down mode, the VOUT(SC2) circuitry is active and monitors for overload conditions on OUT.