JAJSI73C December   2009  – December 2019 BQ24072T , BQ24075T , BQ24079T

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Options
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Undervoltage Lockout (UVLO)
      2. 9.3.2  Overvoltage Protection (OVP)
      3. 9.3.3  Dynamic Power-Path Management
      4. 9.3.4  Battery Charging
      5. 9.3.5  Charge Current Translator
      6. 9.3.6  Battery Detection and Recharge
      7. 9.3.7  Termination Disable (TD Input, BQ24072T)
      8. 9.3.8  Battery Disconnect (SYSOFF Input)
      9. 9.3.9  Dynamic Charge Timers (TMR Input)
      10. 9.3.10 Status Indicators (PGOOD, CHG)
      11. 9.3.11 Thermal Regulation and Thermal Shutdown
      12. 9.3.12 Battery Pack Temperature Monitoring
    4. 9.4 Device Functional Modes
      1. 9.4.1 Input Source Connected (Adapter or USB)
        1. 9.4.1.1 Input DPM Mode (VIN-DPM)
        2. 9.4.1.2 DPPM Mode
        3. 9.4.1.3 Battery Supplement Mode
      2. 9.4.2 Input Source Not Connected
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Using the BQ24075T, BQ24079T to Disconnect the Battery from the System
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Program the Fast Charge Current (ISET):
          2. 10.2.1.2.2 Program the Input Current Limit (ILIM):
          3. 10.2.1.2.3 Program 6.25-hour Fast-Charge Safety Timer (TMR):
          4. 10.2.1.2.4 TS Function:
          5. 10.2.1.2.5 CHG and PGOOD LED Status:
          6. 10.2.1.2.6 Processor Monitoring Status:
          7. 10.2.1.2.7 System ON/OFF (SYSOFF):
          8. 10.2.1.2.8 Selecting IN, OUT and BAT Capacitors
        3. 10.2.1.3 Application Curves
      2. 10.2.2 BQ24072T in a Host Controlled Charger Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedures
          1. 10.2.2.2.1 Termination Disable:
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power On
      1. 11.1.1 Half-Wave Adapters
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Package
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 13.2 関連リンク
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 サポート・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

7 Pin Configuration and Functions

BQ24072T RGT Package
QFN 16 Pin
Top View
BQ24075T and BQ24079 RGT Package
QFN 16 Pin
Top View

Pin Functions

PIN DESCRIPTION
NAME NUMBER I/O
BQ24072T BQ24075T
BQ24079T
TS 1 1 I/O External NTC Thermistor Input. Connect the TS input to the center tap of a resistor divider from VIN to GND with the NTC in parallel with the bottom resistor to monitor the NTC in the battery pack. For applications that do not utilize the TS function, set the resistor divider to be a 20% ratio. See the Battery Pack Temperature Monitoring section for details on calculating the resistor values.
BAT 2, 3 2, 3 I/O Charger Power Stage Output and Battery Voltage Sense Input. Connect BAT to the positive terminal of the battery. Bypass BAT to VSS with a 4.7μF to 47μF ceramic capacitor.
CE 4 4 I Charge Enable Active-Low Input. Connect CE to a high logic level to place the battery charger in standby mode. In standby mode, OUT is active and battery supplement mode is available. Connect /CE to a low logic level to enable the battery charger. CE is internally pulled down with ~285kΩ. Do not leave CE unconnected to ensure proper operation.
EN2 5 5 I Input Current Limit Configuration Inputs. Use EN1 and En2 to control the maximum input current and enable USB compliance. See for the description of the operation states. EN1 and EN2 are internally pulled down with ~285kΩ. Do not leave EN1 or EN2 unconnected to ensure proper operation.
EN1 6 6 I
PGOOD 7 7 O Open-Drain Power Good Status Indication Output. PGOOD pulls to VSS when a valid input source is detected. PGOOD is high-impedance when the input power is not within specified limits. Connect PGOOD to the desired logic voltage rail using a 1kΩ to 100kΩ resistor, or use with an LED for visual indication.
VSS 8 8 – Ground. Connect to the thermal pad and to the ground rail of the circuit.
CHG 9 9 O Open-Drain Charging Status Indication Output. CHG pulls to VSS when the battery is charging. CHG is high-impedance when charging is complete or when the charger is disabled. CHG flashes to indicate a timer fault. Connect CHG to the desired logic voltage rail using a 1kΩ to 100kΩ resistor, or use with an LED for visual indication.
OUT 10, 11 10, 11 O System Supply Output. OUT provides a regulated output when the input is below the OVP threshold and above the regulation voltage. When the input is out of the operation range, OUT is connected to VBAT except when SYSOFF is high. Connect OUT to the system load. Bypass OUT to VSS with a 4.7μF to 47μF ceramic capacitor.
ILIM 12 12 O Adjustable Current Limit Programming Input. Connect a 1.07kΩ to 7.5kΩ resistor from ILIM to VSS to program the maximum input current (EN2=1, EN1=0). The input current includes the system load and the battery charge current. Leaving ILIM unconnected disables all charging.
IN 13 13 I Input Power Connection. Connect IN to the external DC supply (AC adapter or USB port). The input operating range is 4.35V to 6.6V. The input accepts voltages up to 26V without damage, but operation is suspended. Bypass IN to VS with a 1μF to 10μF ceramic capacitor.
TMR 14 14 I Timer Programming Input. TMR controls the pre-charge and fast-charge safety timers. Connect TMR to VSS to disable all safety timers. Connect a 18kΩ to 72kΩ resistor between TMR and VSS to program the timers to a desired length. Leave TMR unconnected to set the timers to the default values.
SYSOFF – 15 I System Enable Input. Connect SYSOFF high to turn off the FET connecting the battery to the system output. When an adapter is connected, charge is also disabled. Connect SYSOFF low for normal operation. SYSOFF is internally pulled up to VBAT through a large resistor (~5MΩ). Do not leave SYSOFF unconnected to ensure proper operation.
TD 15 – I Termination Disable Input. Connect TD high to disable charger termination. Connect TD to VSS to enable charger termination. TD is checked during startup only and cannot be changed during operation. See the TD section in this datasheet for a description of the behavior when termination is disabled. TD is internally pulled down to VSS with ~285 kΩ. Do not leave TD unconnected to ensure proper operation.
ISET 16 16 I/O Fast Charge Current Programming Input. Connect a 590 Ω to 3 kΩ resistor from ISET to VSS to program the fast charge current level. Charging is disabled if ISET is left unconnected. While charging, the voltage ISET reflects the actual charging current and can be used to monitor charge current. See the Charge Current Translator section of this datasheet for more details.
Thermal Pad – -- – There is an internal electrical connection between the exposed thermal pad and the VSS pin of the device. The thermal pad must be connected to the same potential as the VSS pin on the printed circuit board. Do not use the thermal pad as the primary ground input for the device. VSS must be connected to ground at all times.

Table 1. EN1/EN2 Settings

EN2 EN1 MAXIMUM INPUT CURRENT INTO IN
0 0 100 mA. USB100 mode
0 1 500 mA. USB500 mode
1 0 Set by external resistor from ILIM to VSS
1 1 Standby (USB suspend mode)