JAJSIT8 April   2019 PCM1840

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     ブロック概略図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: TDM, I2S or LJ Interface
    7. 6.7 Switching Characteristics: TDM, I2S or LJ Interface
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Hardware Control
      2. 7.3.2 Audio Serial Interfaces
        1. 7.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 7.3.2.2 Inter IC Sound (I2S) Interface
        3. 7.3.2.3 Left-Justified (LJ) Interface
      3. 7.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 7.3.4 Input Channel Configurations
      5. 7.3.5 Reference Voltage
      6. 7.3.6 Microphone Bias
      7. 7.3.7 Signal-Chain Processing
        1. 7.3.7.1 Digital High-Pass Filter
        2. 7.3.7.2 Configurable Digital Decimation Filters
          1. 7.3.7.2.1 Linear Phase Filters
            1. 7.3.7.2.1.1 Sampling Rate: 8 kHz or 7.35 kHz
            2. 7.3.7.2.1.2 Sampling Rate: 16 kHz or 14.7 kHz
            3. 7.3.7.2.1.3 Sampling Rate: 24 kHz or 22.05 kHz
            4. 7.3.7.2.1.4 Sampling Rate: 32 kHz or 29.4 kHz
            5. 7.3.7.2.1.5 Sampling Rate: 48 kHz or 44.1 kHz
            6. 7.3.7.2.1.6 Sampling Rate: 96 kHz or 88.2 kHz
            7. 7.3.7.2.1.7 Sampling Rate: 192 kHz or 176.4 kHz
          2. 7.3.7.2.2 Low-Latency Filters
            1. 7.3.7.2.2.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 7.3.7.2.2.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 7.3.7.2.2.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 7.3.7.2.2.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 7.3.7.2.2.5 Sampling Rate: 96 kHz or 88.2 kHz
      8. 7.3.8 Dynamic Range Enhancer (DRE)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Hardware Shutdown
      2. 7.4.2 Active Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

7.3.3 Phase-Locked Loop (PLL) and Clock Generation

The device uses an integrated, low-jitter, phase-locked loop (PLL) to generate internal clocks required for the ADC modulator and digital filter engine, as well as other control blocks.

In slave mode of operation, the device supports the various output data sample rates (of the FSYNC signal frequency) and the BCLK to FSYNC ratio to configure all clock dividers, including the PLL configuration, internally without host programming. Table 3 and Table 4 list the supported FSYNC and BCLK frequencies.

Table 3. Supported FSYNC (Multiples or Submultiples of 48 kHz) and BCLK Frequencies

BCLK TO FSYNC RATIO BCLK (MHz)
FSYNC
(8 kHz)		 FSYNC
(16 kHz)		 FSYNC
(24 kHz)		 FSYNC
(32 kHz)		 FSYNC
(48 kHz)		 FSYNC
(96 kHz)		 FSYNC
(192 kHz)
16 Reserved 0.256 0.384 0.512 0.768 1.536 3.072
24 Reserved 0.384 0.576 0.768 1.152 2.304 4.608
32 0.256 0.512 0.768 1.024 1.536 3.072 6.144
48 0.384 0.768 1.152 1.536 2.304 4.608 9.216
64 0.512 1.024 1.536 2.048 3.072 6.144 12.288
96 0.768 1.536 2.304 3.072 4.608 9.216 18.432
128 1.024 2.048 3.072 4.096 6.144 12.288 24.576
192 1.536 3.072 4.608 6.144 9.216 18.432 Reserved
256 2.048 4.096 6.144 8.192 12.288 24.576 Reserved
384 3.072 6.144 9.216 12.288 18.432 Reserved Reserved
512 4.096 8.192 12.288 16.384 24.576 Reserved Reserved

Table 4. Supported FSYNC (Multiples or Submultiples of 44.1 kHz) and BCLK Frequencies

BCLK TO FSYNC RATIO BCLK (MHz)
FSYNC
(7.35 kHz)		 FSYNC
(14.7 kHz)		 FSYNC
(22.05 kHz)		 FSYNC
(29.4 kHz)		 FSYNC
(44.1 kHz)		 FSYNC
(88.2 kHz)		 FSYNC
(176.4 kHz)
16 Reserved Reserved 0.3528 0.4704 0.7056 1.4112 2.8224
24 Reserved 0.3528 0.5292 0.7056 1.0584 2.1168 4.2336
32 Reserved 0.4704 0.7056 0.9408 1.4112 2.8224 5.6448
48 0.3528 0.7056 1.0584 1.4112 2.1168 4.2336 8.4672
64 0.4704 0.9408 1.4112 1.8816 2.8224 5.6448 11.2896
96 0.7056 1.4112 2.1168 2.8224 4.2336 8.4672 16.9344
128 0.9408 1.8816 2.8224 3.7632 5.6448 11.2896 22.5792
192 1.4112 2.8224 4.2336 5.6448 8.4672 16.9344 Reserved
256 1.8816 3.7632 5.6448 7.5264 11.2896 22.5792 Reserved
384 2.8224 5.6448 8.4672 11.2896 16.9344 Reserved Reserved
512 3.7632 7.5264 11.2896 15.0528 22.5792 Reserved Reserved

In the master mode of operation, the device uses the MD1 pin (as system clock, MCLK) as the reference input clock source with supported system clock frequency option of either 256 × fS or 512 × fS as configured using the MD0 pin. Table 5 shows the system clock selection for the master mode using the MD0 pin.

Table 5. System Clock Selection for the Master Mode

MD0 SYSTEM CLOCK SELECTION (Valid for Master Mode Only)
LOW System clock with frequency 256 × fS connected to pin MD1 as MCLK
HIGH System clock with frequency 512 × fS connected to pin MD1 as MCLK

See Table 7 and Table 20 for the MD0 and MD1 pin function in the slave mode of operation.