JAJSJ15B October   2020  – March 2022 TPS25947

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
      1.      15
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Reverse Polarity Protection
      2. 8.3.2  Undervoltage Lockout (UVLO and UVP)
      3. 8.3.3  Overvoltage Lockout (OVLO)
      4. 8.3.4  Overvoltage Clamp (OVC)
      5. 8.3.5  Inrush Current, Overcurrent, and Short Circuit Protection
        1. 8.3.5.1 Slew Rate (dVdt) and Inrush Current Control
        2. 8.3.5.2 Circuit-Breaker
        3. 8.3.5.3 Active Current Limiting
        4. 8.3.5.4 Short-Circuit Protection
      6. 8.3.6  Analog Load Current Monitor
      7. 8.3.7  Reverse Current Protection
      8. 8.3.8  Overtemperature Protection (OTP)
      9. 8.3.9  Fault Response and Indication (FLT)
      10. 8.3.10 Auxiliary Channel Control (AUXOFF)
      11. 8.3.11 Power Good Indication (PG)
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Single Device, Self-Controlled
    3. 9.3 Typical Application
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
        1. 9.3.2.1 Device Selection
        2. 9.3.2.2 Setting Undervoltage and Overvoltage Thresholds
        3. 9.3.2.3 Setting Output Voltage Rise Time (tR)
        4. 9.3.2.4 Setting Power Good Assertion Threshold
        5. 9.3.2.5 Setting Overcurrent Threshold (ILIM)
        6. 9.3.2.6 Setting Overcurrent Blanking Interval (tITIMER)
      3. 9.3.3 Application Curves
    4. 9.4 Active ORing
    5. 9.5 Priority Power MUXing
    6. 9.6 USB PD Port Protection
    7. 9.7 Parallel Operation
  10. 10Power Supply Recommendations
    1. 10.1 Transient Protection
    2. 10.2 Output Short-Circuit Measurements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

8.3.11 Power Good Indication (PG)

The TPS259472x, TPS259474x variants provide an active high digital output (PG) which serves as a power good indication signal and is asserted high depending on the voltage at the PGTH pin along with the device state information. The PG is an open-drain pin and must be pulled up to an external supply.

After power up, PG is pulled low initially. The device initiates a inrush sequence in which the HFET is turned on in a controlled manner. When the HFET gate voltage reaches the full overdrive indicating that the inrush sequence is complete and the voltage at PGTH is above VPGTH(R), the PG is asserted after a de-glitch time (tPGA).

PG is de-asserted if at any time during normal operation, the voltage at PGTH falls below VPGTH(F), or the device detects a fault (except overcurrent). The PG de-assertion de-glitch time is tPGD.

GUID-20200915-CA0I-5DR9-MW20-R9KF7W5LBSPF-low.gifFigure 8-17 TPS259472x, TPS259474x PG Timing Diagram
Table 8-5 TPS259472x, TPS259474x PG Indication Summary

Event

Protection Response

PG Pin

PG Delay

Undervoltage (UVP or UVLO)

Shutdown

L

Input Reverse Polarity

Shutdown

L

Overvoltage (OVC)

(TPS259472x only)

Clamp

H (If PGTH pin voltage > VPGTH(R))

L (If PGTH pin voltage < VPGTH(F))

tPGA

tPGD

Overvoltage (OVLO)

(TPS259474x only)

Shutdown

L (If PGTH pin voltage < VPGTH(F))

tPGD

Steady State

NA

H (If PGTH pin voltage > VPGTH(R))

L (If PGTH pin voltage < VPGTH(F))

tPGA

tPGD

Transient overcurrent

NA

H (If PGTH pin voltage > VPGTH(R))

L (If PGTH pin voltage < VPGTH(F))

tPGA

tPGD

Persistent overload (TPS259472x only)

Current Limiting

H (If PGTH pin voltage > VPGTH(R))

L (If PGTH pin voltage < VPGTH(F))

tPGA

tPGD

Persistent overload (TPS259474x only)

Shutdown

L

Output Short-Circuit to GND

Fast trip followed by Current Limit

H (If PGTH pin voltage > VPGTH(R))

L (If PGTH pin voltage < VPGTH(F))

tPGA

tPGD

ILM Pin Open

Shutdown

L (If PGTH pin voltage < VPGTH(F))

tPGD

ILM Pin Shorted to GND

Shutdown

L (If PGTH pin voltage < VPGTH(F))

tPGD

Reverse current ((VOUT – VIN) > VREVTH)

Reverse current blocking

L

tPGD

Overtemperature

Shutdown

L

When there is no supply to the device, the PG pin is expected to stay low. However, there is no active pull-down in this condition to drive this pin all the way down to 0 V. If the PG pin is pulled up to an independent supply which is present even if the device is unpowered, there can be a small voltage seen on this pin depending on the pin sink current, which is a function of the pull-up supply voltage and resistor. Minimize the sink current to keep this pin voltage low enough not to be detected as a logic HIGH by associated external circuits in this condition.