JAJSJ15B October   2020  – March 2022 TPS25947

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
      1.      15
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Reverse Polarity Protection
      2. 8.3.2  Undervoltage Lockout (UVLO and UVP)
      3. 8.3.3  Overvoltage Lockout (OVLO)
      4. 8.3.4  Overvoltage Clamp (OVC)
      5. 8.3.5  Inrush Current, Overcurrent, and Short Circuit Protection
        1. 8.3.5.1 Slew Rate (dVdt) and Inrush Current Control
        2. 8.3.5.2 Circuit-Breaker
        3. 8.3.5.3 Active Current Limiting
        4. 8.3.5.4 Short-Circuit Protection
      6. 8.3.6  Analog Load Current Monitor
      7. 8.3.7  Reverse Current Protection
      8. 8.3.8  Overtemperature Protection (OTP)
      9. 8.3.9  Fault Response and Indication (FLT)
      10. 8.3.10 Auxiliary Channel Control (AUXOFF)
      11. 8.3.11 Power Good Indication (PG)
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Single Device, Self-Controlled
    3. 9.3 Typical Application
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
        1. 9.3.2.1 Device Selection
        2. 9.3.2.2 Setting Undervoltage and Overvoltage Thresholds
        3. 9.3.2.3 Setting Output Voltage Rise Time (tR)
        4. 9.3.2.4 Setting Power Good Assertion Threshold
        5. 9.3.2.5 Setting Overcurrent Threshold (ILIM)
        6. 9.3.2.6 Setting Overcurrent Blanking Interval (tITIMER)
      3. 9.3.3 Application Curves
    4. 9.4 Active ORing
    5. 9.5 Priority Power MUXing
    6. 9.6 USB PD Port Protection
    7. 9.7 Parallel Operation
  10. 10Power Supply Recommendations
    1. 10.1 Transient Protection
    2. 10.2 Output Short-Circuit Measurements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

8.3.9 Fault Response and Indication (FLT)

The following table summarizes the device response to various fault conditions. Additionally, an active low external fault indication (FLT) pin is available on the TPS259470x variants.

Table 8-3 Fault Summary

Event

Protection Response

Fault Latched Internally

FLT Pin Status (1)FLT Assertion Delay(1)

Overtemperature

Shutdown

Y

L

Undervoltage (UVP or UVLO)

Shutdown

N

H

Input Reverse Polarity

Shutdown

N

H

Input Overvoltage

Shutdown(1)(2)

N

H

Voltage Clamp(2)

N

N/A

Transient Overcurrent (ILIM < IOUT < 2 × ILIM)

None

N

N

Persistent Overcurrent

Circuit Breaker(3)

Y

N/A

Persistent OvercurrentCurrent Limit(4)

N

L

tITIMER

Output Short-Circuit to GND

Circuit Breaker followed by Current Limit

N

H

ILM Pin Open

(During Steady State)

Shutdown

N

L

tITIMER

ILM Pin Shorted to GND

Shutdown

Y

L

tITIMER

Reverse Current ((VOUT – VIN) > VREVTH)

Reverse Current Blocking

N

L

(1) Applicable to TPS259470x variants only.
(2) Applicable to TPS259472x variants only.
(3) Applicable to TPS259474x variants only.
(4) Applicable to TPS259470x/2x variants only.

Faults which are latched internally can be cleared either by power cycling the part (pulling VIN to 0 V) or by pulling the EN/UVLO pin voltage below VSD. This also releases the FLT pin for the TPS259470x variants and resets the tRST timer for the TPS25947xA (auto-retry) variants.

During a latched fault, pulling the EN/UVLO just below the UVLO threshold has no impact on the device. This is true for both TPS25947xL (latch-off) and TPS25947xA (auto-retry) variants.

For TPS25947xA (auto-retry) variants, on expiry of the tRST timer after a fault, the device restarts automatically and the FLT pin is de-asserted (TPS259470A variant).